Jai-Hyuk Song

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

Drain current enhancement due to velocity overshoot effects and its analytic modeling

The drain current enhancement due to the velocity overshoot effects is found to be due to the electron velocity enhancement at the source end. Based on this observation, a new analytic model is proposed and verified by two-dimensional (2-D) simulations and experiments. From the results of the verifications, we conclude that our model predicts the drain current enhancement due to the velocity overshoot effects reasonably well. The effects of the device parameters, such as gate oxide thickness and channel doping concentration, on the drain current enhancement ran be readily found in our model.

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).

New Cell Structure with Edge-thick Tunnel Oxide for Highly Reliable NAND Flash Memory Devices

One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is locally thin. For example, conventional SAP (self-aligned poly) process with shallow trench isolation, tunnel oxide at active edge is necessarily thinner than active channel. In this paper, we proposed a new process scheme to fabricate optimized tunnel oxide thickness varying from active center to edge, and we confirmed the improvement of reliability characteristics such as Vth shift and interface trap density during endurance cycling