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Dive into the research topics where Dong-Yean Oh is active.

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Featured researches published by Dong-Yean Oh.


non-volatile memory technology symposium | 2005

3-dimensional analysis on the cell string current of NAND flash memory

H.-S. Oh; Seong-deok Lee; Chang-Sub Lee; Dong-Yean Oh; Tae-Yoon Kim; Jai Hyuk Song; Kyung-Geun Lee; Yoon-dong Park; Joon-hoo Choi; Jeong-Taek Kong

The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD simulation. The geometrical and process parameters are varied and their effects are quantified. It is identified that the coupling ratio has the most significant impact on the cell current and the LDD engineering is more relevant for higher cell current


2006 21st IEEE Non-Volatile Semiconductor Memory Workshop | 2006

New Cell Structure with Edge-thick Tunnel Oxide for Highly Reliable NAND Flash Memory Devices

Tae-Kyung Kim; Jai-Hyuk Song; Chang-Sub Lee; Dong-Yean Oh; Tae-Seok Jang; Jong-Kwang Lim; Dong-jun Lee; Seung Hoon Lee; Minhwan Lim; Hyunyoung Shim; Bong-Tae Park; Man-Ki Lee; Hunkook Lee; Sangyeon Jo; Woon-kyung Lee; Jeong-Hyuk Choi; Kinam Kim

One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is locally thin. For example, conventional SAP (self-aligned poly) process with shallow trench isolation, tunnel oxide at active edge is necessarily thinner than active channel. In this paper, we proposed a new process scheme to fabricate optimized tunnel oxide thickness varying from active center to edge, and we confirmed the improvement of reliability characteristics such as Vth shift and interface trap density during endurance cycling


Archive | 2012

NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME

Dong-Yean Oh; Woon-kyung Lee; Seung-Chul Lee


Archive | 2009

NONVOLATILE SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Dong-Yean Oh; Woon-kyung Lee


2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop | 2007

A New Self-Boosting Phenomenon by Soure/Drain Depletion Cut-off in NAND Flash Memory

Dong-Yean Oh; Chang-Sub Lee; Seung-Chul Lee; Tae-Kyung Kim; Jai-Hyuk Song; Jeong-Hyuk Choi


Archive | 2006

Non-volatile memory device and associated method of manufacture

Dong-Yean Oh; Jeong-Hyuk Choi; Jai-Hyuk Song; Jong-Kwang Lim; Jae-Young Ahn; Ki-Hyun Hwang; Jin-Gyun Kim; H.J. Kim


2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design | 2008

Program Disturb Phenomenon by DIBL in MLC NAND Flash Device

Dong-Yean Oh; Seung-Chul Lee; Chang-Sub Lee; Jai-Hyuk Song; Woon-kyung Lee; Jeong-Hyuk Choi


Archive | 2009

NAND flash memory device and method of operating same to reduce a difference between channel potentials therein

Dong-Yean Oh; Woon-kyung Lee; Jai Hyuk Song; Chang-Sub Lee


Archive | 2009

NAND FLASH MEMORY DEVICE AND METHOD OF OPERATING SAME

Dong-Yean Oh; Woo-Kyung Lee; Jai Hyuk Song; Chang-Sub Lee


Archive | 2011

Methods of fabricating non-volatile memory devices including double diffused junction regions

Dong-Yean Oh; Jai-Hyuk Song; Chang-Sub Lee; Chang-Hyun Lee; Hyun-Jae Kim

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