Erkan Alpman

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

High-speed medium-resolution ADCs are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-VT low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved (TI) Successive-Approximation-Register-based (SAR) ADCs[1] are ideally suited to these applications due to their highly scalable architecture and due to the steady improvement in matching and density of Metal-Finger Capacitors (MFC). This paper presents a TI C-2C SAR ADC that achieves high performance by using: 1) a small-area C-2C SAR architecture with low input capacitance; 2) high-speed boosted switches to overcome high device threshold; 3) background comparator offset calibration and radix calibration; and 4) redundant-ADC-based gain, offset and timing calibration to reduce TI errors.

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.

An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS

A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer

This paper presents an energy-efficient third-order 3 bit continuous-time delta-sigma modulator (CTDSM). In this work, several architectural and circuit techniques are adopted to facilitate a low-power modulator. In the loop filter design, a single-amplifier biquad (SAB) topology is incorporated to realize the desired transfer function. With the SAB architecture, only two amplifiers are needed for implementing a third-order CTDSM. Furthermore, in the proposed SAB, the excess-loop-delay (ELD) compensation is implemented without using an extra summing circuit. For the 3 bit quantizer, a time-domain quantizer is proposed, where the data-weighted-averaging function is embedded in this quantizer to mitigate the nonlinearity issue due to the mismatch of digital-to-analog converter (DAC) unit cells. Fabricated in a 90 nm CMOS technology and clocked at 300 MHz sampling frequency, the proposed SAB-based modulator achieves a 67.2 dB SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit of 135 fJ/conversion-step.

A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN

A clock-skew tolerant 8-bit 16x time-interleaved (TI) semi-synchronous SAR ADC with switching-energy efficient hybrid resistive-capacitive DAC is presented that meets WiGig standard requirements with only background offset and gain calibrations. Skew tolerance is achieved by using a “correct-by-construction,” timing-calibration-free global bottom-plate sampling scheme. The ADC achieves a sampling rate of 2.64 GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40 nm LP CMOS design dissipates 39 mW from 1.2 V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44 dB EVM at sensitivity with a QAM16 signal.

A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

A clock-skew tolerant 8-bit 16x time-interleaved (TI) SAR ADC is presented that meets WiGig standard requirements with only background offset and gain calibrations. By using a “correct-by-construction”, timing-calibration-free global bottom-plate sampling scheme, the ADC achieves a sampling rate of 2.64GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40nm LP CMOS design dissipates 39mW from 1.2V. The TI-SAR ADC characterized with an integrated receiver front-end achieves -21.44dB EVM at sensitivity with an OFDM/ QAM16 signal.

95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS

A 2.4GHz fully-integrated Wi-Fi compliant wake-up receiver in 14nm FinFET technology is presented. The receiver achieves −72dBm sensitivity and +20dBr adjacent channel interference rejection for 62.5kbps at 10−3 BER while consuming 95µW. The OOK-modulated wake-up packet can be transmitted using any legacy OFDM Wi-Fi transmitter.

A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS

A 4th-order 4-bit continuous-time delta-sigma modulator (CTDSM) employing single-amplifier biquad (SAB) based loop filter and an interpolating quantizer is presented. By adopting the SAB-based topology, the proposed loop filter achieves 4th-order noise shaping function with only two op-amps. Furthermore, the proposed twin-T SAB minimizes the latency of the excess loop delay (ELD) compensation path (s0) and 1st-order path (s-1), which achieves better system stability. A low-power interpolating flash quantizer with an embedded random-skip incremental data weighted averaging (RS-IDWA) function is also proposed to address the nonlinearity of the quantizer and feedback DACs. With this technique, signal-dependent harmonic tones induced by the conventional DWA are avoided. Fabricated in a 90-nm CMOS, the proposed CTDSM achieves a peak SNDR of 68 dB over 13-MHz signal bandwidth, while consuming 5.1 mW at 320-MHz sampling frequency. The FoM is 95 fJ/conv.-step.