Brent R. Carlton

Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband Applications

Extremely compact resistive-feedback CMOS low-noise amplifiers (LNAs) are presented as a cost-effective alternative to multiple narrowband LNAs using high-Q inductors for multiband wireless applications. Limited linearity and high power consumption of the inductorless resistive-feedback LNAs are analyzed and circuit techniques are proposed to solve these issues. A 12-mW resistive-feedback LNA, based on current-reuse transconductance boosting is presented with a gain of 21 dB and a noise figure (NF) of 2.6 dB at 5 GHz. The LNA achieves an output third-order intercept point (IP3) of 12.3 dBm at 5 GHz by reducing loop-gain rolloff and by improving linearity of individual stages. The active die area of the LNA is only 0.012 mm2. A 9.2-mW tuned resistive-feedback LNA utilizing a single compact low-Q on-chip inductor is presented, showing an improved tradeoff between performance, power consumption, and die area. At 5.5 GHz, the fully integrated LNA achieves a measured gain of 24 dB, an NF of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2-V supply and has a 3-dB bandwidth of 3.94 GHz (4.04-7.98 GHz). The LNA occupies a die area of 0.022 mm2. Both LNAs are implemented in a 90-nm CMOS process and do not require any costly RF enhancement options.

A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Transistors in aggressively scaled CMOS technologies have fT greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm2 active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

An × 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

A highly linear filter and VGA chain with novel DC-offset correction in 90nm digital CMOS process

This paper presents a complete base-band chain for current and emerging WLAN in 1.4V 90nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 1/10/100MHz filter and five VGA stages. The design is DC-offset free and uses optimized Gm stages for linearity and low voltage operation. IIP3 is 2dBm @ 13.5dB minimum gain, while dissipating 13.5mW.

A 1.4V, 13.5mW, 10/100MHz 6/sup th/ order elliptic filter/VGA with DC-offset correction in 90nm CMOS [WLAN applications]

This paper presents a complete base-band chain for WLAN applications in 1.4 V 90 nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 10/100 MHz filter and five VGA stages. The design is DC-offset free and uses optimized transconductance for linearity and low-voltage operation. Moreover, the integrators in the filter are compensated for losses through a frequency transformation. The IIP3 is 2 dBm at 13.5 dB minimum gain, while dissipating 13.5 mW.

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS

A 5GHz 2times2 MIMO transceiver in 90nm CMOS supports spatial multiplexing and diversity, achieving 54/108Mb/s with -75/-63dBm sensitivity for an AWGN/25ns-Rayleigh channel, respectively. Each RX draws 120mA from a 1.4V supply. Each 3.3V 5GHz PA delivers +16/+13dBm average power with -25/-27dB EVM in 1times1/2times2 modes, respectively. The system-in-package including microstrip front-end matching on a flip-chip package occupies a die area of 18mm2

A 1.4V, 2.4/5 GHz, 90nm CMOS system in a package transceiver for next generation WLAN

We present a 2.4/5GHz system in a package transceiver with integrated 5GHz PA and 10-100MHz signal bandwidth, suitable for next generation WLAN applications. The RXs achieve better than -71dBm sensitivity for 64 QAM while drawing 120mA from a 1.4 supply in a 90nm CMOS process. The integrated 3.3V, 5GHz PA delivers 9dBm average power with an EVM better than -25dB. The transceiver incorporates de-convolved calibration of quadrature mismatches in the transmitter and receiver for improved performance and yield. Micro strip passives are integrated into a flip chip package for both LNA and PA matching elements.

Low-Cost Direct Conversion RF Front-Ends in Deep Submicron CMOS

This paper reviews architectures and circuit techniques suitable for highly integrated broadband receiver front-ends. Direct conversion simplifies the receiver architecture, resistive feedback LNAs reduce silicon area and current mode passive mixer operation improves the receiver linearity and reduces flicker noise. A 2-5.8 GHz receiver front-end dissipating 85 mW at 5 GHz while occupying 0.2 mm2 active area is fabricated as a demonstration of the combination of these concepts. It provides 44 dB of gain, 3.4 dB double side band noise figure, -21 dBm iIP3 and -15 dB of input matching.

32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver

Embedded PC applications are growing, driven by their cost, performance and software compatibility. The SoC described in this work is a unique device designed for rapid integration and customization for specific market segments. A rich multi-source IP eco-system consisting of standardized interfaces, modular and configurable building blocks, enables automation and fast execution to deliver a broad range of targeted solutions. Integrating high-performance digital circuits with analog and RF circuits on a leading edge process enables our SoC architecture to increase the level of integration, performance and reduce the cost of the platform. WiFi has remained an external PC component due to the challenges of managing system noise from the digital circuits. This paper presents an integrated standard x86 OS compliant, dual-core ATOM® processor-based SoC, including the RF WiFi to drive down platform cost. Key enabling features are: (a) a 32nm RF process with HV transistors and RF passives; (b) an on-chip interconnect fabric for modularity; (c) a clock generator with SSC to reduce substrate noise injection and EMI; (d) voltage regulators for power management and rail reduction; (e) an 802.11b/g RF WiFi transceiver with integrated LNA, PA, T/R switch and BIST/calibration engine.

A 9.2 mW, 4-8 GHz Resistive Feedback CMOS LNA with 24.4 dB Gain, 2 dB Noise Figure, and 21.5 dBm Output IP3

A 9.2 mW resistive feedback CMOS low-noise amplifier with a 3-dB bandwidth of 3.94 GHz (4.04 -7.98 GHz) is presented. At 5.5 GHz, the fully integrated LNA achieves a measured gain above 24 dB, a noise figure of 2 dB, and an output IP3 of 21.5 dBm. The LNA draws 7.7 mA from the 1.2 V supply and utilizes a single compact low-Q on-chip inductor. The LNA is implemented in a 90-nm CMOS process and occupies a die area of only 0.022 mm2.