Chang-Wook Jeong

Programming characteristics of phase change random access memory using phase change simulations

We present a new simulation methodology for analyzing programming characteristics of a chalcogenide based phase-change device, phase change random access memory (PRAM), which is a next-generation non-volatile memory. Using the new simulation methodology, we analyze the initialization of chalcogenide material (ICM) of the mechanism and propose the next generation PRAM scheme. From the results of the phase change simulation, the process conditions for ICM for stable operation are presented. Also, the self-heating confined structure to overcome the inherent limitation of high operation power is proposed that resolves the operating power limitation associated with PRAM development.

Fabrication of Cu/Co bilayer gate electrodes using selective chemical vapor deposition and soft lithographic patterning

A templated Cu/Co bilayer gate electrode was fabricated using the combined method of consecutive and selective chemical vapor deposition (CVD), and octadecyltrichlorosilane (OTS) microcontact printing techniques. Soft lithographically patterned self-assembled monolayers (SAMs) can direct the growth of Co occurring at the low temperatures 50–90 °C and serve as a template for the consecutive and selective growth of Cu, thereby forming stable and high quality Cu/Co bilayer gate electrodes on a glass substrate. This simple process provides fewer process steps and higher performance than other conventional processes, and can be applied to the fabrication of large area and high resolution thin film transistor liquid crystal displays.

Physical understanding of alloy scattering in SiGe channel for high-performance strained pFETs

For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1-3], so the accurate modeling of alloy scattering in SiGe channel has become an important issue to predict the performance of future SiGe-based FETs. Usually, the calculation of alloy scattering mobility assumes an alloy scattering center in a simple analytical form with some fitting parameters, which is a good practical approach but has a limited predictability. In this paper, an atomistic tight-binding simulation is used to study alloy scattering in SiGe-based FETs, and to compare with experimental data. We conclude (i) although it is essentially impossible to avoid alloy scattering in SiGe material, (ii) high-mobility is indeed achieved in SiGe channel by combining lattice-mismatch stresses from Si virtual substrate with stresses from Source/Drain(SD) stressor.

Enhanced adhesion and performance of the source/drain electrode using a single-layered Ag(Cu) film for an amorphous silicon thin-film transistor

The feasibility of using a Ag(Cu) alloy film as a source/drain electrode for thin-film transistor (TFT) liquid-crystal displays has been investigated. The annealing of a Ag(Cu)/Si structure, for 30 min at 200 °C, produced a uniform Cu3Si layer at the Ag(Cu)–Si interface, as a result of the reaction of the segregated Cu with Si. This lowered the resistivity from 5.3 to 3.2 μΩ cm, which also led to improved adhesion properties. A hydrogenated amorphous silicon (a-Si:H) TFT was fabricated using a single layer of Ag (19 at. % Cu) alloy film as the source/drain metal. The subthreshold slope, mobility, and threshold voltage obtained from the fabricated a-Si:H TFT were 0.78 V/dec, 0.79 cm2/V s, and 2 V, respectively, revealing a reduction in the process steps, with excellent performance.

Highly Strained Si pFinFET on SiC With Good Control of Sub-Fin Leakage and Self-Heating

Investigating of ON-current boosting, short channel effect (SCE), and self-heating effect in Si pFinFET on a SiC stress relaxed buffer (SRB) layer is presented compared with SiGe pFinFET on a SiGe-SRB. Both SiC-SRB-based device and SiGe-SRB-based device show mobility boosting due to high compressive channel stress as well as enhanced SCE due to significant suppressing of subfin leakage. However, if self-heating is considered, SiGe-based devices exhibit non-negligible current degradation compared to SiC-SRB-based devices. Even though SiGe channel devices on a SiGe-SRB show better performance compared with SiC-SRB-based device, it is shown that the impact of BEOL reliability should be considered carefully.

Nanoscale-nMOSFET junction design: Quantum transport approach

Employing quantum transport solver, we have demonstrated the impact of junction proximity and abruptness on device performance. To entail the discrete dopant effect accurately, impurity scattering has been introduced in non-perturbative way. The electrostatic metrics and effective current have been evaluated for practical dimensions and technologically relevant junctions. A simple guideline for junction design has been concluded.