Won-Cheol Jeong

Full integration and reliability evaluation of phase-change RAM based on 0.24 /spl mu/m-CMOS technologies

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

Writing current reduction for high-density phase-change RAM

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

Highly scalable MRAM using field assisted current induced switching

A novel MRAM structure using current induced switching is implemented and evaluated. The current for switching, assisted by local field, was 1mA with 19 % magneto-resistance at 100 mV bias voltage. 0.2/spl times/0.3 /spl mu/m/sup 2/ magnetic elements were integrated with standard CMOS process and a magnetic tunnel junction was optimized to obtain enough sensing signal. The resistance of tunnel junction was controlled to improve sensing margin. The novel structure has the possibility of reducing cell size to 6F, in which digit lines are unnecessary, and can minimize the writing disturbance. This novel structure is the excellent candidate for MRAM as one of universal memory.

Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

A process integration of high performance 64 Kb MRAM

In this paper, magnetic and electrical properties of the MTJs have been investigated at each fabrication step of the full integration with carefully designed parameters of M-H and I-V properties and TMR properties of 64Kb MRAM with minimal process induced damages have been achieved.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

Fully integrated 64 Kb MRAM with novel reference cell scheme

We have fully integrated a 64 Kb MRAM with 0.24 /spl mu/m-CMOS technology. A new sensing scheme employing a separated half-current source is adopted for the reference bit line to increase the sensing signal. To reduce cell resistance, a Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of the buffer layer, on which the MTJs are stacked, is reduced by using Ru on the TiN bottom electrode, and magnetic disturbance is avoided by depositing TiN hard masks on the MTJ under low-power and low-temperature conditions. The tunneling barrier micro-bridge due to the attachment of by-products during etching is completely eliminated by adopting a 2-step MTJ etch with an introduced capping oxide layer. Consequently, MR values of >30% are found in more than 90% of chips.

A new reference signal generation method for MRAM using a 90-degree rotated MTJ

A new reference signal generation method for high-density MRAM is reported. 0.4/spl times/0.8 /spl mu/m/sup 2/ magnetic tunnel junction (MTJ) elements were successfully integrated with 0.24-/spl mu/m CMOS technology. By using a 90-degree rotated MTJ as a new reference signal generator, the reference resistance could be always located in the exact midpoint between high-resistance state R/sub H/ and low-resistance state R/sub L/ regardless of applied voltage. When tested in 8/spl times/8 MTJ arrays, it is found to show good fidelity to our expectations. So it is supposed that this new method is more favorable for high-density MRAM.

Field assisted spin switching in magnetic random access memory

A switching method called by field assisted spin switching has been investigated. A field assisted spin switching consists of a metal line induced magnetic field and a spin switching through a magnetic tunnel junction. It is a variation of a current induced switching and assisted by the magnetic field induced by the current-carrying metal line. Various current paths have been tested to investigate how and how much the spin switching contributes to the overall switching and the results will be explained. A computer simulation has been complemented to measure the degree of the thermal effect in the switching.