ByungKyu Cho

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

Fabrication of Cu/Co bilayer gate electrodes using selective chemical vapor deposition and soft lithographic patterning

A templated Cu/Co bilayer gate electrode was fabricated using the combined method of consecutive and selective chemical vapor deposition (CVD), and octadecyltrichlorosilane (OTS) microcontact printing techniques. Soft lithographically patterned self-assembled monolayers (SAMs) can direct the growth of Co occurring at the low temperatures 50–90 °C and serve as a template for the consecutive and selective growth of Cu, thereby forming stable and high quality Cu/Co bilayer gate electrodes on a glass substrate. This simple process provides fewer process steps and higher performance than other conventional processes, and can be applied to the fabrication of large area and high resolution thin film transistor liquid crystal displays.

A new floating gate cell structure with a silicon-nitride cap layer for sub-20 nm NAND flash memory

A new cell structure of NAND memory devices, which employs an additional nitride layer between the top of a floating gate (FG) and inter-poly dielectrics (IPD), is devised to lesson a high electric field on the FG top edges during program. The cell structure is proved to be promising in sub-20 nm NAND generation in terms of larger program window, better endurance, and more robust data retention, which are obtained by decreasing a leakage current of IPD relating with the electric field on the FG top edges.

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate

NAND flash memory is widely used as a cost-effective storage with high performance [1-2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640μs program time and a 800MB/s I/O rate is achieved.