Yoonsuk Hyun

Dependence of EUV Mask Printing Performance on Blank Architecture

EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. This paper deals with the investigation of the impact of the mask blank architecture on the wafer print by EUV lithography. Presently the material stack on the mask is not fixed and different suppliers offer a range of variation. The purpose of the present paper is threefold, as detailed hereafter. First it is shown that there are possibilities to make EUV masks less prone to reflectivity loss by carbon contamination. An estimate is given for the required limitations on mask contamination and fabrication tolerance to keep the imaging impact below acceptable levels. These data can be used as preliminary error budgets for the individual and combined capping layer deterioration phenomena. Further-on, printing results on the Alpha Demo Tool (ADT) are reported, obtained with different reticles with identical layout produced on blanks with different mask stacks. In preparation for this experimental work simulations have been undertaken. The experimental results show good agreement in printing performance between the reticles tested. Finally, our work clearly shows the opportunity to reduce the absorber thickness without noticeable loss of contrast and with the big advantage of shadowing effect reduction.

Evaluation of shadowing and flare effect for EUV tool

One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography. In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirks disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.

Feasibility of EUVL thin absorber mask for minimization of mask shadowing effect

Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns by simulation. However various reports have been presented on mask shadowing bias correction, experimental results are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which allows us less shadowing effect with minimum loss of process window. In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V CD bias and process window will be presented.

Comparative study of DRAM cell patterning between ArF immersion and EUV lithography

In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around 40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been examined intensively. However, double patterning and spacer patterning technology are not cost-effective process because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore, lithography community is looking forward to improving maturity of EUVL technology. In order to overcome several issues on EUV technology, many studies are needed for device application. EUV technology is different characteristics with conventional optical lithography which are non-telecentricity and mask topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern direction, pattern type and slit position of target pattern.1 For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch. Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.

EUV mask particle adders during scanner exposure

As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.

EUV mask defect analysis from mask to wafer printing

ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.

Practical flare compensation strategy for DRAM device

Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real device is measured experimentally with real device layout with clearing pads in it. Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.

EUV-patterning characterization using a 3D mask simulation and field EUV scanner

In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node. EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing effect and flare level are one of the important issues for EUV lithography. In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and space pattern is calculated.

Hyper NA polarized imaging of 45nm DRAM

In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated through experiment. Process window and mask error enhancement factors are measured with respect to various design rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool - corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally. Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.

Feasibility study of printing sub 100 nm with ArF lithography

The feasibility of sub-100 nm patterning with ArF lithography has been studied. We used ArF 0.63 NA exposure tool and investigated process windows. In-house resist (DHA-H110) and bottom anti-reflective coating material (HEART004) are used as well as commercial ones. To print sub-100 nm patterns we used the resolution enhancement technology (RET) that is extreme off-axis illumination (OAI) such as dipole and strong annular. To predict the result and compare with experimental data our simulation tool HOST (Hyundai OPC Simulation Tool) based on diffused aerial image model (DAIM) was used. Although the infrastructure of ArF lithography is not mature enough, we got a good result. For 95 nm and 90 nm patterns we could get more than 8% exposure latitude (EL) and 0.3 micrometer depth of focus (DOF). For isolated gate pattern sub-70 nm pattern was printed and we have got the characteristics of 70 nm periphery transistor. For contact hole (C/H) patterns it was more effective to use KrF lithography because resist thermal flow process (RFP) can be used to shrink C/H size. With RFP we printed up to 50 nm C/H patterns. Through this study we found that k1 value can be reduced up to 0.29 and ArF lithography can be applied for 70 nm node with high contrast resist and high NA exposure tool.