Hyeong Soo Kim

4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure

For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.

NbO 2 -based low power and cost effective 1S1R switching for high density cross point ReRAM Application

In this paper, 5Xnm cross point cell array for the low power ReRAM operation was developed with 1S1R cell structure. Through the optimization of both TiOx/TaOx based-1R and NbO2 based-1S stacks with TiN based-electrode, the worlds first and best bipolar switching characteristics with the lowest operation current (20~50uA) and sneak current (~1uA) level were acquired.

The Implementation Of Sub-150nm Contact Hole Pattern By Resist Flow Process

The characteristics and performance of the resist flow process (RFP), which is one of the contact hole (C/H) shrinking technologies, were investigated for sub-150 nm C/H patterns using KrF (λ=248 nm) lithography. A fine C/H pattern was defined by adopting optimized process parameters at a higher baking temperature than the glass transition temperature of the used matrix material. The shrinking limit of the C/H pattern was in the range of 40–50 nm without any deformation in profile from the original C/H size, however, the bowing profile of the C/H pattern was observed in the case of a shrinking bias larger than 50 nm. It was also found that the amount of shrinkage of the C/H pattern was strongly dependent on the baking temperature, total quantity of the resist surrounding the C/H pattern, and resist thickness. When the 150 nm C/H pattern was formed by RFP from a 180 nm C/H generated by an attenuated phase shifting mask (PSM), the depth of focus (DOF) and the energy latitude (EL) were 1.6 µm and 16%, respectively, and the critical dimension (CD) uniformity in an 8-inch wafer was less than 25 nm. In this study, in spite of baking to enable resist flow, the etch selectivity of resist on silicon substrates was not changed and the C/H pattern on silicon oxide after the etching process showed a vertical profile. Based on these results, it is believed that the RFP for a sub-150 nm C/H pattern will be a very promising candidate for the mass production of gigabit devices.

Low power switching of Si-doped Ta2O5 resistive random access memory for high density memory application

We report, for the first time, the resistive switching properties of Si-doped Ta2O5 grown by atomic layer deposition (ALD). The reduced switching current, improved on/off current ratio, and excellent endurance property are demonstrated in the Si-doped Ta2O5 resistive random access memory (ReRAM) devices of 50 nm tech node. The switching mechanism for the Si-doped Ta2O5 resistor is discussed. Si dopants enable switching layer to have conformal distribution of oxygen vacancy and easily form conductive filament. This leads to higher on/off current ratio at even low operation current of 5–10 µA. Finally, one selector–one resistor (1S1R) ReRAM was developed for large cell array application. For the optimized 1S1R stack, 0.2 µA of off current and 5.0 of on/off current ratio were successfully achieved at 10 µA of low operation current.

Improvement of characteristics of NbO2 selector and full integration of 4F2 2x-nm tech 1S1R ReRAM

In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.

Practical flare compensation strategy for DRAM device

Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real device is measured experimentally with real device layout with clearing pads in it. Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.

High performance low A/R poly PN diode for 20nm node PCRAM cell switch

High performance 20nm-node PCRAM cell switching was successfully realized with the remarkable Ion/Ioff characteristics employing low aspect ratio poly PN diode on metal. Nice Ion/Ioff ratio was obtained by modifying stack of diode adopted in-situ boron-doped poly SiGe and thermal optimization with spike RTA. Basically, boron has high solubility and activation rate in SiGe matrix. In-situ boron-doped poly SiGe on P+ region is expected to contribute to P+ Rc improvement. In this study, we found the unusual phenomenon that thermal process after pillar patterning does not influence dopant diffusion due mainly to isotropic thermal behavior. It means that RTA process before pillar patterning will be more effective for doping profile and activation engineering. By applying spike RTA and in-situ boron-doped poly SiGe on diode, P+ Rc was not degraded despite of skipping additional P+ADD IMP and P+ ADD RTA process. As a result, Ion and Ioff of 393uA/cell on the 2.8V and 92pA/cell on the -3.5V at 75°C were achieved at height of diode down to 1000Å.

Implementation of KrF 0.29 k1 lithography

One of the crucial tasks of semiconductor process is reduction of manufacturing cost by shrinking the design rule with the help of fine patterning technologies. For high density DRAM application, we explored 0.29 k1 lithography with KrF 0.80NA scanner. Well-known lithography technologies such as asymmetric crosspole, dipole illumination and 6% attenuated PSMs were used for this experiment. Illumination source and mask layout optimization were carried out iteratively to meet CD target, and high contrast thin resist was applied to improve pattern fidelity. Some of the biggest challenges were coping with large MEEF and reducing simulation error. Abnormal non-open fail, probably due to large MEEF, was observed at a dense contact hole pattern. To cope with non-open fail, we tested multi-PSM which composed of alternating PSM along the x-axis direction and 6% attenuated PSM along the y-axis direction. Also we pushed sigma offset of illumination pupil more strongly than exposure tools specification and there was no serious drawbacks of partial coherency extension. Accurate partial coherence measurement was important for obtaining target CDs and reducing OPC error. For some layers, unexpected simulation error was occurred especially at the patterns of peripheral circuit, therefore we had to calibrate simulation parameters of in-house tool and commercial tool (Solid-C) for OPC simulation. Finally we successfully demonstrated 0.29k1 KrF lithography by showing process yield over 58% in 512Mb DRAM having design rule of 90nm. Based on the results we obtained, we can conclude that 0.29k1 lithography is quite feasible for mass production and 60nm design rule DRAM devices can be manufactured with ArF dry 0.93NA. Since dry 0.93NA corresponds to 1.33NA in ArF water immersion with respect to k1, we can expect that it is possible to fabricate 42nm DRAM devices with ArF immersion lithography.

Effects of Resist Thickness and Substrate Reflectance on Critical Dimension Bias of Isolated-Dense Pattern

The critical dimension (CD) uniformity of an isolated-dense pattern has been the most critical issue in optical lithography below the wavelength of the illumination source and much effort has been exerted to improve it. The CD difference between isolated and dense patterns (ID bias), which is caused by proximity effects, is known to be one of the key factors leading to the deterioration of CD uniformity. Because ID bias is such a complicated phenomenon and affected by many factors, it would be very difficult to control it even though we understand all the factors that lead to it. Much research on ID bias has been conducted; however, the effect of resist thickness on ID bias has not yet been clearly studied. From our investigations, we have investigated the effects of resist thickness on ID bias and found that ID bias is strongly affected by resist thickness. ID bias changes periodically with resist thickness and the minimum ID bias is obtained by controlling the resist thickness for a specified pattern. We also found that the antireflective coating (ARC) process is an effective method for controlling ID bias.

Heterogeneous diffusion model for simulation of resist process

There have been imposed quite incompatible requirements on lithographic simulation tool for OPC, that is it should be enough accurate and enough fast. Though diffused aerial image model (DAIM) has achieved these goals successfully, rapid transition of lithography into very low k1 and sub-resolution regime makes it very difficult to meet these goals without loss of any of speed or accuracy. In this paper we suggested new modeling method of resist process which is called heterogeneous diffusion of aerial image. First, various examples of CD discrepancy between experiment and simulation with DAIM are suggested. Then the theoretical background of new model is explained and finally CD prediction performance of new model is demonstrated in 60nm 0.29k1 patterning of real DRAM devices. Improved CD prediction capability of new model is observed in various critical patterning of DRAM.