Changwook Yoon

System-on-package ultra-wideband transmitter using CMOS impulse generator

In this paper, a low-cost CMOS ultra-wideband (UWB) impulse transmitter module with a compact form factor is proposed for impulse-radio communications. The module consists of a CMOS impulse generator, a compact bandpass filter (BPF), and a printed planar UWB antenna. The impulse generator is designed using a Samsung 0.35-/spl mu/m CMOS process for low-cost and low-power fabrication. The measurement shows the fabricated chip makes a train of sharp triangular pulses with a peak voltage of about 2.8 V under the supply voltage of 3.3 V. To make an impulse fit the Federal Communications Commission (FCC) spectrum mask, the compact BPF is developed using a coupled strip line and a tapered stub. Also, the compact planar UWB antenna is developed. All of the components of the UWB transmitter module are fabricated on a single package using system-on-package technology for miniaturization. The proposed UWB transmitter is tested in an office environment. The measured results show that the generated UWB signal meets the FCC regulation, and the peak-to-peak amplitude of received UWB signal at 1-m distance on line of sight is 16 mVpp with a 10-dB-gain low-noise amplifier in the receiver.

Analytical Probability Density Calculation for Step Pulse Response of a Single-Ended Buffer With Arbitrary Power-Supply Voltage Fluctuations

An analytical methodology to calculate the probability density functions (PDFs) for the step pulse response of a single-ended buffer with arbitrary power-supply voltage fluctuations is proposed. To validate the theory, a silicon IC with noise-aggressing buffers and a victim buffer was designed, fabricated, and assembled in a printed circuit board (PCB). The overall power distribution network (PDN) of the IC and PCB was modeled from impedance measurements. The PDFs of the step pulse response of the victim buffer with power-supply voltage fluctuations were calculated and validated by comparisons with HSPICE and experimental results. The obtained PDFs due to power-supply voltage fluctuations could be combined with the statistical link simulation methods for quick estimation of bit error rate (BER).

Design criteria of automatic fixture removal (AFR) for asymmetric fixture de-embedding

Automatic fixture removal (AFR) for asymmetric fixture de-embedding is introduced. Two design criteria for fixture design in AFR, passivity and discontinuity, are proposed. Three different 2x-fixtures are investigated for the verification of proposed two design criteria.

Design of UWB Transceiver SiP for Short Range Communication

Since UWB system uses a wide frequency range from 3.1 GHz to 5.1 GHz, package parasitic effects have been a hot issue which affects system malfunction. To prevent such malfunction, SiP technology is adjusted considering not only a circuit performance but various design issues in a package from viewpoints of signal integrity and power integrity. Furthermore, UWB band-pass filter is embedded into a package to reduce a complexity of transmitter circuit and the power consumption. Designed UWB SiP performance is verified by the measurement in time domain.

Design Criteria and Error Sensitivity of Time-Domain Channel Characterization (TCC) for Asymmetry Fixture De-Embedding

Time-domain channel characterization (TCC) for de-embedding of an asymmetric fixture is introduced. Two design criteria for the design of a 2x-thru are proposed. Error sensitivity regarding a small error in the S-parameters of the 1x-fixture is analyzed with an insertion loss error-coefficient and a return loss error-coefficient. The TCC procedure, including proposed design criteria and error sensitivity, is also introduced to reduce the error in the TCC application. Three different 2x-thru structures are investigated for the verification of the two proposed design criteria and analyzed for error sensitivity. Test fixtures on a printed circuit boards are fabricated for the experimental verification.

On-chip voltage regulator module (VRM) effect on power/ground noise and jitter at high-speed output buffer

On-chip voltage regulator module (VRM) for the reduction of power/ground noise on power distribution network (PDN) and jitter minimization at high-speed output buffer is introduced. The basic topology and optimized operation for on-chip VRM is analyzed. A PDN with on-chip VRM shows reduced power/ground noise through removing additional effects coming from package/PCB PDN. Also, when on-chip VRM is implemented on PDN of high-speed output buffers, jitter at output signal is lower. Improvements on PDN and jitter through on-chip VRM are shown and validated with SPICE simulation with 110nm CMOS technology library.

Analysis of the Effect of AC Noise on DC Bias of VGA for UHF RFID using Chip-package Co-modeling and Simulation

Ever since radio frequency identification (RFID) was first introduced, the demand for smaller and low-power-consuming RFID system never stopped increasing. Many researchers dealt and successfully reduced the size. But as the size of and RFID system is reduced, the noise coupling between blocks became more severe. Especially, when noise is coupled to variable gain amplifier (VGA) block, the output may be damaged and lead to failure in reading tags. But finding and simulating sources and effect of noise is very complicated and time consuming. Thus, it is crucial to model and simplify the system. In this paper, the noise and its effect on VGA for UHF RFID is modeled, simulated, and modeled.

Substrate design optimization for high performance small form factor flip chip ball grid array (FCBGA) packages

This work summarizes the multiple design and development activities within Intel to optimize the real estate for FCBGA packaging technology. The advantages made are part of the cost saving solutions to enable high performance small form factor flip chip ball grid array (FCBGA) substrate. Key focus areas include challenges in enabling ultra mini 0402/0201 die side capacitor (DSC), optimizing transfer media or material handling system, optimizing assembly and test tooling design for smaller and cheaper substrate design.

Impact of Die Pin Capacitance and Package Crosstalk on DDR4 Channel Jitter

Design of memory I/O channels or general purpose I/O (GPIO) has become very complicated as we aim for higher speeds, higher I/O count and cost-effective solutions. At these speeds, package and die discontinuities cause more deterministic jitter and noise due to inter-symbol interference (ISI) effects and crosstalk. Therefore, to improve timing margins, engineers have to carefully study impact of package and die capacitive/inductive discontinuities in order to improve the portion contributing to eye diagram closure. This paper specifically shows how these discontinuities affect DDR4 memory system simulations differently based on the direction of communication, that is, Write (die to DRAM) and Read (DRAM to die) and then offers practical solutions that can be used to mitigate jitter and improve margins.

Impact of Channel Loading to Power Distribution Network Designs

A PDN consisting of lumped elements is passive and linear to the frequency variation. However, adding active drivers to the PDN is easily distorted depending on load conditions at the end of a signal channel. Depending on two major states in a push-pull driver, pull-up versus pull-down, the load affects the passive PDN, resulting in a non-linear PDN profile. This non-linearity is demonstrated in this paper of the first time. We investigate the non-linear behavior for various signaling schemes in both frequency and time domains along with different load conditions.