Chao-Ching Hung

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μs without and with the modified bang-bang algorithm, respectively.

93.5∼109.4GHz CMOS injection-locked frequency divider with 15.3% locking range

A distributed-LC injection-locked frequency divider is proposed. This frequency divider has been realized in 65 nm CMOS technology. The core area is 0.036 mm2. The measured operation range is 93.5~109.4 GHz. Its center frequency is 102 GHz and the locking range is 15.3%. Its power is 5.5 mW from the supply of 1.1 V.

A Leakage-Compensated PLL in 65-nm CMOS Technology

A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm2.

A Noise Filtering Technique for Fractional-

A noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order delta-sigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metal-oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz.

N

In nanoscale CMOS processes, the leakage current [1,2] is becoming one of the important issues to cope with for high-performance analog and mixed-signal integrated circuits. For digital circuits, the leakage current results in a high stand-by power consumption. For analog circuits, it degrades the accuracy and performance. PLLs are widely used in various wireline and wireless communication systems. For a phase/frequency detector (PFD) and a divider in a PLL, the leakage current increases the in-band phase noise and jitter. For a VCO, the leakage current alters the common-mode voltage, and as a result the VCO may not operate at a low frequency [3]. For a charge pump (CP) and a loop filter, the leakage current induces a steady phase error and jitter. It is because the leakage current charges or discharges the loop filter while the CP is off. Since a PLL usually needs a large capacitor in its loop filter, the MOS capacitor is often used to save the area. However, the large MOS capacitor suffers from the large leakage current in a nanoscale CMOS process. An analog method to suppress the leakage current for the MOS capacitor is reported in [4]. This method works well under a low leakage current. However, once the leakage current is large enough, e.g., several 100µA, an operational amplifier with a high current-drive capability is required.

Frequency Synthesizers

A 33.6-33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 11 -1 PRBS. The measured bit error rate is less than 10-8 for a 33.72 Gb/s, 27 -1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.

A leakage-suppression technique for phase-locked systems in 65nm CMOS

A fast-locked all-digital phase-locked loop (PLL) with supply noise suppression is presented. The analysis and design of this all-digital PLL is presented. While the supply noise exits, the loop bandwidth of this all-digital PLL is dynamically adjusted to suppress the jitter. This all-digital PLL is fabricated in a 0.18um CMOS process. It achieves the locked time of 22.5us and 78us with and without the fast-locked circuit, respectively. The measured peak-to-peak jitter and rms jitter are 38.9ps and 5.9ps, respectively, at 1.25GHz.

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A delay-locked loop (DLL) Integrated with an analog self-calibration circuit is presented. The proposed DLL can generate precise multiphase clocks over process corners, voltage/temperature variations and device mismatches when incorporating with the calibration circuit and variable-delay output buffers. The experimental circuit in a standard 0.35-mum CMOS process demonstrates delay mismatch between phases can be reduced from tens of pico-second to less than ten pico-seconds at 100 MHz. The prototype circuit occupies an area of 2.1 mm2, and consumes around 10.1 mW at 3.3 V.

A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression

A 35.56GHz all-digital phase-locked loop with high resolution varactors is presented. To enhance the frequency resolution for a high-frequency digitally controlled oscillator, the proposed varactor with its body connected to digital control bits is presented. A 35.56GHz all-digital PLL is realized in 90nm CMOS process. The measured peak-to-peak jitter and rms jitter are 3.84ps and 349.1fs, respectively, at 35.56GHz.

A Self-Calibrated Multiphase DLL-Based Clock Generator

In this paper, a 57.1-59 GHz fractional-N frequency synthesizer has been fabricated in 90 nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12 dB with the same PLL bandwidth. It consumes 89 mW from a 1.2 V analog supply with output buffers and 16 mW from a 1.2 V digital supply. The chip occupies 0.86 times1.28 mm2 and the measured phase noise at 58.359375 GHz with the offset frequency of 2 MHz is -95.1 dBc/Hz.