Lan-u Cho

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter

We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low power consumption. A transmitter (TX) employs an all-digital PLL (ADPLL) with switched-current-source digitally controlled oscillator (DCO) and switching PA. An integrated on-chip matching network serves both PA and LNTA, thus allowing a 1-pin direct antenna connection with no external antenna filters. The transceiver consumes 2.75mW in RX and 3.6mW in TX when delivering 0 dBm in Bluetooth LE.

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm

We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter is realized in 28nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5mW while delivering 0dBm/3 dBm RF power in Bluetooth Low-Energy.

A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We demonstrate the scheme with two 4GHz digitally controlled oscillators (DCO) separated by 650um on a 16nm CMOS die, mutually coupled via a differential transmission line and injection-locked to a 125MHz reference. The proposed architecture achieves a sub-ps calibrated skew with 87fs rms jitter while consuming 4.3mW, resulting in −258dB clock FOM (jitter2 × power).