Chihun Lee

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS

A 58-60.4GHz frequency synthesizer is implemented in a 90nm CMOS process. A VCO with a distributed-LC tank and a current-reuse frequency divider are used. For 60.4GHz, the measured phase noise at 1 MHz and 2MHz offset is -85.1dBc/Hz and -95dBc/Hz, respectively. Including the buffers, the chip consumes 80mW from a 1.2V supply.

A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13-

A 37-38.5-GHz clock generator is presented in this paper. An eight-phase LC voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass characteristic CL ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and enhances the gain. To verify the function of each block and modify the operation frequency, two additional testing components-an eight-phase VCO and a split-load frequency divider-are fabricated using 0.13-mum CMOS technology. The measured quadrature-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13-mum CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is -97.55 dBc/Hz at 1-MHz offset frequency

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A 33.6-33.8 Gb/s burst-mode clock/data recovery circuit (BMCDR) is presented in this paper. To reduce the data jitter and generate the high-frequency output clock, the LC gated voltage-controlled oscillator is presented. To receive and transmit the broadband data, a wideband input matching circuit and a wideband data buffer are presented, respectively. The phase selector is proposed to overcome the false phase lock due to the full-rate operation. This proposed BMCDR has been fabricated in a 90 nm CMOS process. The measured peak-to-peak and rms jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, for a 33.72 Gb/s, 2 11 -1 PRBS. The measured bit error rate is less than 10-8 for a 33.72 Gb/s, 27 -1 PRBS. It consumes 73 mW without buffers from a 1.2 V supply.

m CMOS Technology

A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from a 1.2V supply excluding the buffers.

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology

A 35Gb/s limiting amplifier using cascaded-distributed amplifiers with active feedback and on-chip transformers achieves a differential gain SDD21 of 38 dB and a bandwidth of 26.2GHz. It has been fabricated in 0.13mum CMOS technology. It exhibits a single-ended output swing of 300mVPP while consuming 125mW from a 1.5V supply

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS

A dual-band 61.4~63 GHz/75.5~77.5 GHz receiver has been realized in a 90 nm CMOS technology. It is composed of a broadband low-noise amplifier, RF/IF mixers, and a quadruplicate-locked phase-locked loop. With the dual down-conversion approach, this dual-band receiver achieves a conversion voltage gain of 25.2 dB at 62.5 GHz and 19.4 dB at 77 GHz with an input P1dB of -16 dBm. It consumes 132 mW from a 1.5 V supply.

A 35-Gb/s Limiting Amplifier in 0.13/spl mu/m CMOS Technology

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.

A dual-band 61.4∼63GHz/75.5∼77.5GHz CMOS receiver in a 90nm technology

A 37-38.5GHz octave-phase clock generator is presented. An octave-phase LC voltage-controlled oscillator and the split-load divider are presented. The proposed PD improves the static phase error and enhances the gain. The clock generator has been fabricated in 0.13mum CMOS technology. It achieves the rms jitter of 0.24ps at 38GHz while consuming 51.6mW without buffers from a 1.2V supply

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-

A differential distributed amplifier employs a loss-compensation L section to increase the bandwidth of the interstage by a factor of 3.5. To demonstrate the proposed circuit, a cascaded distributed amplifier with five stages is presented. It has been fabricated in a 0.18um CMOS process and achieves a gain of better than 15 dB and a pass bandwidth of 100 MHz to 25.5 GHz while consuming 171 mW from a 1.9-V supply

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In this paper, a 57.1-59 GHz fractional-N frequency synthesizer has been fabricated in 90 nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12 dB with the same PLL bandwidth. It consumes 89 mW from a 1.2 V analog supply with output buffers and 16 mW from a 1.2 V digital supply. The chip occupies 0.86 times1.28 mm2 and the measured phase noise at 58.359375 GHz with the offset frequency of 2 MHz is -95.1 dBc/Hz.