Chao Wang

HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs

A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.

An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 μm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis.

A fast and energy-efficient level shifter with wide shifting range from sub-threshold up to I/O voltage

This paper presents a fast and energy-efficient current mirror based level shifter with wide shifting range from sub-threshold voltage up to I/O voltage. Small delay and low power consumption are achieved by addressing the non-full output swing and charge sharing issues in the level shifter from [4]. The measurement results show that the proposed level shifter can convert from 0.21V up to 3.3V with significantly improved delay and power consumption over the existing level shifters. Compared with [4], the maximum reduction of delay, switching energy and leakage power are 3X, 19X, 29X respectively when converting 0.3V to a higher voltage between 0.6V and 3.3V.

BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems

This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits.

Near-Threshold Energy- and Area-Efficient Reconfigurable DWPT/DWT Processor for Healthcare-Monitoring Applications

This brief presents an energy- and area-efficient discrete wavelet packet transform (DWPT) processor design for power-constrained and cost-sensitive healthcare-monitoring applications. This DWPT processor employs recursive memory-shared architecture to achieve low hardware complexity while performing required arbitrary-basis DWPT decomposition. By exploiting inherent characteristics of different physiological signals through an entropy statistic engine, the DWPT processor core can be reconfigured to compute multilevel wavelet decomposition with effective time and frequency resolution. Various design techniques from algorithm to circuit levels, including reconfigurable computing, lifting scheme, dual-port pipeline processing, near-threshold operation, and clock gating, are applied to achieve energy efficiency. With a 0.18-μm CMOS technology at 0.5 V and 1 MHz, the DWPT core only consumes 26 μW for performing three-level 256-point DWPT decomposition with entropy statistic calculation. When integrated in an ARM Cortex-M0-based biomedical system-on-a-chip test platform, the DWPT processor achieves processing acceleration by three orders of magnitude and reduces energy consumption by four orders of magnitude compared with CPU-only implementations.

Ultra-low-energy near-threshold biomedical signal processor for versatile wireless health monitoring

In this paper, an ultra-low-energy biomedical signal processor (BSP) is proposed for wireless multi-channel physiological signal monitoring. This BSP integrates a RISC core and application-specific hardware accelerators (ASHAs) to achieve ultra low power consumption while meeting required performance. Various low power design techniques from system to circuit levels are applied, including event-driven signal processing, dynamic clock management, near-threshold operation, glitch-free clock generation, fine-grain clock gating, and ultra-low-voltage level shifting. The BSP can operate with supply from 1.8V down to 0.5V. With integrated ECG ASHAs based on the discrete wavelet transform, its overall energy consumption is 20.4pJ/cycle at 0.5V and 10MHz when performing a real-time wireless ECG monitoring.

A 457-nW cognitive multi-functional ECG processor

In this paper, a multi-functional ECG signal processor for wearable and implantable real-time monitoring is presented. To enable extremely long-term ambulatory monitoring, several power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An on-chip low-complexity cardiac signal analysis module is proposed to realize comprehensive analysis functions. Near-threshold circuit technique is applied to the overall system. Implemented in 0.18 μm CMOS, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V supply for real-time ambulatory monitoring. Compared with existing designs, the presented ECG processor achieves the lowest power consumption.

Fast and energy-efficient low-voltage level shifters

This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65nm shows that both of the proposed level shifters achieve significantly better performance (up to 12i?) and energy consumption (up to 8i?) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains.

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively.