Charles C. Kuo

A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is presented. Its double gate, thin body structure reduces dopant fluctuation effects, off-state leakage, and disturb problems. The cells large body coefficient amplifies small gains of body potential into increased drain current. Experimental measurements of DG-DRAM were made using recessed channel SOI n-MOSFETs. No significant degradation in programming, retention, and read behavior was observed after 10/sup 11/ cycles. Cell geometry, operating voltages, and material quality should be considered for DG-DRAM in embedded and stand-alone applications. The feasibility of DG-DRAM in future high density CMOS memories depends on issues such as manufacturability, soft error reliability, and tail bit distribution.