Mark L. Doczy

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

Recently there has been tremendous progress made in the research of novel nanotechnology for future nanoelectronic applications. In particular, several emerging nanoelectronic devices such as carbon-nanotube field-effect transistors (FETs), Si nanowire FETs, and planar III-V compound semiconductor (e.g., InSb, InAs) FETs, all hold promise as potential device candidates to be integrated onto the silicon platform for enhancing circuit functionality and also for extending Moores Law. For high-performance and low-power logic transistor applications, it is important that these research devices are frequently benchmarked against the existing Si logic transistor data in order to gauge the progress of research. In this paper, we use four key device metrics to compare these emerging nanoelectronic devices to the state-of-the-art planar and nonplanar Si logic transistors. These four metrics include: 1) CV/I or intrinsic gate delay versus physical gate length L/sub g/; 2) energy-delay product versus L/sub g/; 3) subthreshold slope versus L/sub g/; and 4) CV/I versus on-to-off-state current ratio I/sub ON//I/sub OFF/. The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome. We believe that benchmarking is a key element in accelerating the progress of nanotechnology research for logic transistor applications.

Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS trigate transistors are demonstrated with IDSAT=1.4 mA/mum and 1.1 mA/mum respectively (IOFF=100nA/mum, VCC =1.1V and LG=40nm) with excellent short channel effects (SCE)-DIBL and subthreshold swing, DeltaS. The contributions of strain, the lang100rang vs. lang110rang substrate orientations, high-k gate dielectrics, and low channel doping are investigated for a variety of channel dimensions and FIN profiles. We observe no evidence of early parasitic corner transistor turn-on in the current devices which can potentially degrade ION-IOFF and DeltaS

CMOS-compatible synthesis of large-area, high-mobility graphene by chemical vapor deposition of acetylene on cobalt thin films.

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C(2)H(2)) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO(2)/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm(2)/V s and ∼1000 cm(2)/V s, respectively, and a low trap density of ∼1.2 × 10(11) cm(-2).

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.

Gate dielectric scaling for high-performance CMOS: from SiO 2 to high-K

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.

Silicon nano-transistors for logic applications

Abstract Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15 nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.

Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications

Sustaining Moores Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moores Law will continue at least through early next decade. By combining silicon innovations with other nanotechnologies on the same Si platform, it is expected that Moores Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotubefield-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.

Advanced Si and SiGe strained channel NMOS and PMOS transistors with high-k/metal-gate stack

Sustaining Moores Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.

Emerging silicon and nonsilicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications

Several key emerging nanoelectronic devices, such as Si nanowire field-effect transistors (FETs), carbon nanotube FETs, and III-V compound semiconductor quantum-well FETs, are assessed for their potential in future high-performance, low-power computation applications. Furthermore, these devices are benchmarked against state-of-the-art Si CMOS technologies. The two fundamental transistor benchmarking metrics utilized in this study are: (i) CVII versus L/sub G/; and ii) CVII versus I/sub ON//I/sub OFF/. While intrinsic device speed is emphasized in the first metric, the tradeoff between device speed and off-state leakage is assessed in the latter. For high-performance and low-power logic applications, low CVII and high I/sub ON//I/sub OFF/ values are both required. Based on the results obtained, the opportunities and challenges for these emerging novel devices in future logic applications are highlighted and discussed.

Graphene field-effect transistors using large-area monolayer graphene grown by chemical vapor deposition on Co thin films

There has been great interest in methods for the synthesis of high-quality, large-area graphene films, as required for practical applications in the electronics industry. In particular, recent developments in chemical vapor deposition (CVD) methods have shown a promising approach to grow large-area graphene on metal substrates by catalyzed CVD growth [1]. Reports of CVD growth on Cu and Ni are common [1–3]; however, there have been few efforts to grow graphene on Co [4], and attempts to grow graphene on Co/SiO2/Si resulted in very small domains of predominantly multilayer graphene that were not suitable for transistor fabrication. Unlike Ni, Co is attractive due to the low lattice mismatch (< 2%) between graphene and the Co (0001) surface, and Co exhibits greater compatibility with Si than Cu, which is a deep trap in Si and a fast diffuser. Here we have demonstrated graphene field-effect transistors (GFETs) fabricated using large-area monolayer graphene grown by catalyzed CVD on Co films.