Charles F. Machala

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs.

A submicron DC MOSFET model for simulation of analog circuits

This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of g/sub D/ with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do not predict the effects of gate and substrate bias adequately. A new smoothing function is used to unify the linear and saturation regions in a single expression. Continuity of transconductance is maintained between the weak and strong inversion regions. Model efficiency is maintained by avoiding the use of transcendental functions in the smoothing techniques. We demonstrate >

Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields.

Investigation and Modeling of Fluorine Co-Implantation Effects on Dopant Redistribution

A comprehensive model is developed from ab-initio calculations to understand the effects of co-implanted fluorine (F) on boron (B) and phosphorus (P) under sub-amorphizing and amorphizing conditions. The depth of the amorphous-crystalline interface and the implant depth of F are the key parameters to understand the interactions. Under sub-amorphizing conditions, B and P diffusion are enhanced, in contrast to amorphized regions where the model predicts retarded diffusion. This analysis predicts the F effect on B and P to be entirely due to interactions of F with point-defects.

Effect of nitride sidewall spacer process on boron dose loss in ultrashallow junction formation

A nitride spacer with an underlying deposited tetraethoxysilane oxide, that behaves as a convenient etch stop layer, is a popular choice for sidewall spacer in modern complementary metal–oxide–semiconductor process flows. In this work we have investigated the effect of the silicon nitride spacer process on the boron profile in silicon and the related dose loss of B from the Si into the silicon dioxide. This is reflected as a dramatic decrease in the junction depth. We find that the silicon nitride influences the concentration of hydrogen in the silicon dioxide during the final source/drain anneal. The presence of H enhances the diffusivity of B in the silicon dioxide and thereby results in a significant dose loss from the Si into the silicon dioxide. In this work we have shown this dose loss can be lowered by altering the silicon nitride stoichiometry.

An efficient algorithm for the extraction of parameters with high confidence from nonlinear models

Analytical models with parameters numerically extracted from I-V data have been used in simulation of MOS circuits. The equations are quasi-physical and the extracted parameters do not normally relate to any single identifiable physical mechanism. We have developed an extraction system that can provide a measure of the level of confidence in the extracted parameters; hence, these parameters may be reliably used in circuit simulation as well as process control. The algorithm described is model independent and can be used for any nonlinear least-squares parameter extraction problem.

A Physical Understanding of RF Noise in Bulk nMOSFETs With Channel Lengths in the Nanometer Regime

Experimental and simulation results of high-frequency channel noise in MOSFETs with 40-, 80-, and 110- nm gate lengths are presented. The measured dc I-V characteristics can be matched using the drift-diffusion (DD) and hydrodynamic (HD) transport models, both incorporating velocity saturation. The DD model grossly underestimates the measured noise, demonstrating the inadequacy of channel-length modulation and impact ionization to explain the excess noise. The HD model generates higher noise but not enough, showing that introduction of carrier heating is still insufficient to explain the experimental results. The underprediction of noise using the HD model can be mitigated by a suitable choice of the energy relaxation time and saturation velocity; however, simultaneous matching of both noise and dc I-V does not produce satisfactory results. Thus, TCAD simulators are unable to simulate this excess-noise mechanism at this time. Experimental data support that, at 40 nm gate lengths, noise can be described by a shot noise like expression.

Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions

A novel model is developed to explain the effect of the source/drain sidewall spacer process on boron drain extension formation. A diffusion model for hydrogen in the source/drain sidewall spacer is developed and combined with a model for boron diffusion in oxides. The model is first calibrated to hydrogen out-diffusion data from Nuclear Reaction Analysis (NRA) and then to boron diffusion data from Secondary Ion Mass Spectroscopy (SIMS). Seemingly anomalous changes in boron junction depths with variation in sidewall spacer deposition conditions are explained by this model. The model is applied to TCAD process/device simulations to understand the effect of sidewall spacer on CMOS device performance.