Periannan Chidambaram

Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing

Semiconductor industry has increasingly resorted to strain as a means of realizing the required node-to-node transistor performance improvements. Straining silicon fundamentally changes the mechanical, electrical (band structure and mobility), and chemical (diffusion and activation) properties. As silicon is strained and subjected to high-temperature thermal processing, it undergoes mechanical deformations that create defects, which may significantly limit yield. Engineers have to manipulate these properties of silicon to balance the performance gains against defect generation. This paper will elucidate the current understanding and ongoing published efforts on all these critical properties in bulk strained silicon. The manifestation of these properties in CMOS transistor performance and designs that successfully harness strain is reviewed in the last section. Current manufacturable strained-silicon technologies are reviewed with particular emphasis on scalability. A detailed case study on recessed silicon germanium transistors illustrates the application of the fundamentals to optimal transistor design.

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs.

Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields.

Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions

A novel model is developed to explain the effect of the source/drain sidewall spacer process on boron drain extension formation. A diffusion model for hydrogen in the source/drain sidewall spacer is developed and combined with a model for boron diffusion in oxides. The model is first calibrated to hydrogen out-diffusion data from Nuclear Reaction Analysis (NRA) and then to boron diffusion data from Secondary Ion Mass Spectroscopy (SIMS). Seemingly anomalous changes in boron junction depths with variation in sidewall spacer deposition conditions are explained by this model. The model is applied to TCAD process/device simulations to understand the effect of sidewall spacer on CMOS device performance.

Modeling of Diffusion and Activation of Low Energy Arsenic Implants in Silicon

In summary, we find it is possible to model the extent of arsenic diffusion during front-end and back-end processes that define the final junction depth. The key features of the model can be summarised as: (a) Interstitials from implant damage play a diminished role as implant energies are scaled; (b) As 4 V formation and precipitation at high concentrations is critical to accurate modeling of ultra-shallow arsenic junctions. These models when used with device simulations help optimize transistor performance/tradeoffs. We would like to thank Pavel Fastenko and Scott T. Dunham (University of Washington) for details and discussion regarding their modeling results.

Probing Nanoscale Local Lattice Strains in Advanced Si CMOS Devices by CBED: A Tutorial with Recent Results

The experimental methodology to characterize the nanoscale local lattice strain in advanced Si CMOS devices by using Focused Ion Beam (FIB) system and Convergent Beam Electron Diffraction (CBED) is discussed. Through both high spatial resolution of Transmission Electron Microscopy (TEM) and high strain sensitivity of the CBED technique, compressive lattice strains in the order of 10 -3 from the nanoscale Si PMOS channel region are detected. The one-dimensional quantitative strain-mapping is performed by obtaining and simulating high quality CBED patterns with different zone axes such as and .

Continuum Modeling of Indium to Predict SSR Profiles

Indium (In) diffusion and dose-loss in silicon is modeled in a continuum simulator. The model includes the large segregation of In to End of Range (EOR) defects, and the dissolution of these defects resulting in dose-loss of In at the surface. The models developed are successfully applied to predict state of the art (90 nm) transistor performance.