Charles Njinda

Optimal Seguencing of Scan Registers

Due to the high cost of test equipment, reducing the test time of a device is important. Scan designs require a large test application time. We present a methodology to construct a single scan chain that provides dramatic reductions in test application time. The main idea as t o order the scan registers in the chain so as to enable easy access to registers that are frequently used. In conjunction with a novel test application scheme, we provide an algorithmic technique to generate single chain configurations that minimize the test time. Implementation results highlighting the advantages of the proposed methodology are presented.

Generating a family of testable designs using the BILBO methodology

There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.

A systematic approach for designing testable VLSI circuits

A systematic approach has been developed to provide designers with a set of testable versions for a given design, ranging from the minimal test time solution to the minimal area overhead solution. The designer thus has the flexibility to make the necessary tradeoff between area overhead and test time depending on the constraints of the design under consideration. By employing an expert selection developed previously, the system can be extended to operate as an intelligent BIST (built-in self-test) design advisor. Experiments have been performed on several circuits generated by MABAL, a high-level synthesis tool, to demonstrate the performance of this approach.<<ETX>>

SIESTA: a multi-facet scan design system

Scan design methodology has led to a range of design-for-testability techniques. However, scan techniques are not universally accepted by circuit designers because of the various overheads involved, such as chip area, performance, I/O pin count and test application time. The authors present a multi-facet scan design system called SIESTA that attempts to find solutions that satisfy designer goals and constraints. SIESTA incorporates a range of methodologies and optimization techniques that deal with the issues of partial scan, circuit partitioning, test application and scan path chaining. It employs several new concepts that do not exist in other scan design systems.<<ETX>>

SWiTEST: a switch level test generation system for CMOS combinational circuits

Switch level test generation (SLTG) is potentially more powerful than conventional gate level test generation (GLTG) or CMOS circuits. Over the last decade much research has been carried out on SLTG. However to date no widely accepted SLTG system exists. The objectives of this work are to analyze the various problems associated with SLTG, to identify a feasible way to deal with these problems, and to develop an efficient and useful SLTG system for combinational circuits. The basic idea is to make use of as many GLTG concepts as possible without modeling a CMOS circuit at the gate level. Based on the analysis of CMOS circuits and faults, a SLTG system called SWiTEST has been developed. This system can deal with bridging, transistor stuck-open, transistor stuck-on and stuck-at faults. It employs both logic and current (IDDQ testing) monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework of this system is PODEM-based. To be applicable to switch level circuits, the basic PODEM algorithm has been enhanced to deal with concepts such as multiple objective selection, search-based backtracing and incremental event-driven logic implication. Experimental results indicate that SWiTEST is quite efficient in both CPU time and memory usage. >

Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware

The authors present a procedure for merging on-chip controllers for BIST (built-in self-test) circuitry to reduce hardware overhead. Instead of starting with one minimal state assignment and then performing state, input, and output encoding, one picks the 1-hot code state assignment and implicitly searches the space of minimum prime compatible state covers to obtain an optimal merged controller. This procedure uses knowledge of the greatest lower bounds on states, arcs, next-state, and the output logic of the merged controller to prune the search space.<<ETX>>

A hierarchical DFT architecture for chip, board and system test/debug

This work presents the Procket DFT architecture which is developed to improve manufacturability (time-to-market, high quality and ease of chip/board/system bring-up) thus reducing the time for chip ramp and initial system bring-up. Common DFT structures are used on all chips in the family and a similar process is used to access all on-chip DFT structures from the system. This architecture allows for reconfigurable scan chains, which includes parallel chains for tester access, and various sections of the chains during board/system bring up to allow for easy diagnosis. Access to all debug features is via the IEEE 1149.1 ports which allows the same software to be used for chip, board and system debug.

A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing

Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<<ETX>>