Che-Yu Yang

Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation

Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation Chun-Hao Tu, Ting-Chang Chang,* Po-Tsun Liu, Hsiao-Wen Zan, Ya-Hsiang Tai, Che-Yu Yang, Yung-Chun Wu, Hsin-Chou Liu, Wei-Ren Chen, and Chun-Yen Chang Institute of Electronics, National Chiao Tung University, Taiwan Department of Physics and Institute of Electro-Optical Engineering, Center for Nanoscience, Nanotechnology, National Sun Yat-sen University, Kaohsiung Taiwan National Nano Device Laboratories, Taiwan

The relaxation of intrinsic compressive stress in complementary metal-oxide-semiconductor transistors by additional N ion implantation treatment with atomic force microscope-Raman stress extraction

Based on the stress extraction and measurement by atomic force microscope-Raman technique with the nanometer level space resolution, the high compressive stress about 550 MPa on the Si active region (OD) is observed for the current complementary metal-oxide-semiconductor (CMOS) transistor. During the thermal budget for the standard manufacture process of the current CMOS transistor, the difference of thermal expansion coefficients between Si and Shallow Trench Isolation (STI) oxide results in this high compressive stress in Si OD and further degrades the electron carrier mobility seriously. In order to relax this intrinsic processed compressive stress in Si OD and try to recover this performance loss, the novel process is proposed in this work in addition to the usage of one-side pad SiN layer. With this novel process of additional N-ion implantation (IMP) treatment in STI oxide, it can be found that the less compressive stress about 438 MPa in Si OD can be achieved by the smaller difference of thermal ex...

The systematic study and simulation modeling on nano-level dislocation edge stress effects

The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal-oxide-semiconductor field-effect transistors is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si OD region with and without dislocation edge stress treatment is extracted by atomic force microscope-Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the STI intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM-Raman spectra experimentally, the simulated stress from prop...

Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation

Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than 5 X 10 15 cm -2 , however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.

A novel stress design for the type-II hetero-junction solar cell with superior performance

High efficient surface textured SiGe-based solar cell is proposed by the designed top nano-level surface trench structure and the optimized SiGe/Si type-II substrate hetero-junction design. The surface reflectance rate of solar cell can be successfully reduced about 3 times (totally from 32% to ∼10%) by the nano-surface textured structure with obvious photonic crystal effect, simulated by finite differential time domain simulation. With different top surface trench spacing (d) structure design on the nanometer level, broadband antireflection and total absorption rate can be realized and enhanced greatly, respectively. Moreover, SiGe/Si hetero-structure substrate is also implemented to enhance an additional solar cell efficiency about 3% in this work, not only due to the originally higher absorption rate in SiGe-based material but also due to optimized SiGe/Si type-II hetero-structure substrate design. The offset and discontinuousness of the energy band between n+-Si and grown fully strained Si0.9Ge0.1 typ...

Improved Performance of F-Ions-Implanted Poly-Si Thin-Film Transistors Using Solid Phase Crystallization and Excimer Laser Crystallization

Polycrystalline silicon thin-film transistors (Poly-Si TFTs) with F-ions-implantation were investigated in this study. The electrical characteristics and reliability of the F-ions-implanted poly-Si TFTs were reported for solid phase crystallization (SPC) and excimer laser crystallization (ELC) methods respectively. The thermal annealing causes F-ions to pile up at the poly-Si interface, without the initial pad oxide deposition. With the introduction of fluorine in poly-Si film, the trap state density was effectively reduced. Also, the presence of strong Si-F bonds enhances electrical endurance against hot carrier impact by using F-ions-implantation. These improvements in electrical characteristics are even obvious for the ELC poly-Si TFTs compared to the SPC ones

Influence of thermal annealing on the electron emission of InAs quantum dots containing a misfit defect state

We have investigated the effect of postgrowth thermal annealing on the electron emission from InAs quantum dots (QDs) containing a misfit-related defect state induced by strain relaxation. Additional carrier depletion in the GaAs bottom layer near the QD, caused by the defect state, can effectively suppress electron tunneling from the QD, leading to the observation of a thermal emission from the QD electron ground state to the GaAs conduction band with a large emission energy of 213 meV, in contrast to defect-free nonrelaxed QDs in which an emission of 58 meV from the QD electron ground state to first excited state is observed. The emission energy is reduced to 193 meV and to 164 meV after annealing at 650 and 700 °C for 1 min, respectively. This emission energy reduction is correlated with the photoluminescence blueshift which is attributed to the interdiffusion of atoms across the QD interface. The electron emission from the QD first excited and ground states is found to be a thermal emission at high te...

Strain relaxation in InAs self-assembled quantum dots induced by a high N incorporation

The effect of a high N incorporation in self-assembled InAs quantum dots (QDs) is investigated by analyzing the electronic and structural properties around QD region. Capacitance-voltage profiling and admittance spectroscopy shows that N incorporation into the InAs QD layer leads to drastic carrier depletion in the QD layer and neighboring GaAs layers due to the formation of a deep defect state at 0.34–0.41 eV. The signature of this defect state is similar to those defects observed in strain relaxed QDs or InGaAs/GaAs quantum wells when the InAs deposition thickness exceeds a critical thickness. Accordingly, the N incorporation might result in strain relaxation either by increasing localized strain or by inducing composition inhomogeneities, which provide nucleation sources for strain relaxation. The argument of strain relaxation is supported by transmission electron microscopy that reveals lattice misfits at the QD layer and neighboring GaAs layers.