Chen-Han Chou

Low-Leakage Tetragonal ZrO 2 (EOT In Situ Plasma Interfacial Passivation on Germanium

We successfully fabricated gate stacks (ZrO2/GeOx/Ge) with a subnanometer equivalent oxide thickness (EOT) and low-leakage current on n-/p-Ge through plasma-enhanced atomic layer deposition (ALD). A 0.78-nmthick GeOx was formed through plasma oxidation (i.e., in situ plasma interfacial passivation, followed by 3.48-nm-thick ZrO2 growth in the same ALD reactor). A subnanometer EOT of N0.9 nm was achieved with a relatively high dielectric constant (roughly 30) of tetragonal-phase ZrO2. The gate leakage was N1 x 10-4 A/cm2 at VFB - 1 V, and roughly 5 x 10-5 A/cm2 at VFB t 1 V on pand n-type Ge, respectively. Our ZrO2 stabilized in the tetragonal phase, when the post-deposition annealing temperature, was higher than 500 °C. Therefore, the proposed scheme is simple and effective for use in pursuing an ultralow EOT gate dielectric on Ge.

Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs

This paper presents a high-performance Ge p-channel MOSFET (pMOSFET) with NiGePt as a ternary-phase alloy of Schottky source/drain (S/D) formed through low-temperature microwave-activated annealing (MWA). We fabricated a NiGePt alloy contact with uniform crystallinity through structural engineering and MWA. We clarified the phenomena of thermal reaction and diffusion for forming ternary-phase alloys using MWA properties such as thermal dynamics and ionic transportation. The ternary-phase NiGePt alloy is crucial for improving the off-leakage current of the junction. A lower process temperature is beneficial for eliminating surface roughness and reducing alloy agglomeration of the Schottky contact S/D. Consequently, the fabricated NiGePt/n-Ge Schottky junction exhibited a high effective barrier height (ΦBn) of 0.59 eV, resulting in a high junction current ratio of more than 105 at an applied voltage of |Va| = 1 V. In addition, we exploited the advantages of low-temperature microwave annealing to fabricate the pMOSFET, which includes a GeO2 passivation layer and a Schottky S/D. Our ternary Schottky Ge pMOSFET (L = 4μm) exhibited high ION/IOFF ratios of approximately 3.7 × 103 (ID) and 1.3 × 105 (IS) and a moderate subthreshold swing of 126 mV/dec.

3D-TCAD simulation study of the contact all around T-FinFET structure for 10nm metal-oxide-semiconductor field-effect transistor

We propose a new device structure, namely CAA T-FinFET, for 10nm MOSFETs with using contact all around (CAA) structure. According to 3D simulation study, the CAA T-FinFET possess many advantages over the conventional FinFET structure, such as short channel effect (SCE) suppression by self-aligned oxide (SA oxide), parasitic leakage path isolation with body-tied bulk, source/drain series resistance reducing and fin to fin pitch scaling by contact all around process. Base on heterogeneous bulk for strain application, CAA T-FinFET has better electrical performance and easy process control. All these advantages are achieved by depositing a self-aligned oxide after isotropic etching in S/D region. Contact all around can efficiently solve the series resistance degradation and pitch scaling by replacing diamond-shape S/D stressor with the full contact metal. CAA T-FinFET has high potential to be applied to the varied heterogeneous substrate and high mobility channel (Ge and III-V) MOSFETs by SA oxide.

Improving Thermal Stability and Interface State Density of High-

We propose a new HfGeO_x interfacial layer (IL) for the high-κ gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeO_x IL. We inserted an additional HfO2 layer after the formation of GeO_x in the HfO₂/Al₂O₃/GeO_x/Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 °C. We speculate that the improvement originates from the formation of HfGeO_x through the combination of HfO₂ and GeO_x, according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high-κ gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density (D_it) of approximately 3.3×10¹¹ eV^-1 cm^-2, and an impressive gate leakage current of approximately 2.2 × 10^-6 A/cm² at V_FB -1V.

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In this paper, a method that entails using microwave thermal oxidation to form a high-quality gate dielectric on Ge through surface passivation at considerably low temperatures (<400 °C) is presented. Formation of the GeOx layer was confirmed by x-ray photoelectron spectroscopy. To reduce the bulk trap density and interface trap density (Dit), microwave thermal oxidation was employed for postdeposition microwave thermal oxidation after the deposition of Al2O3 through atomic layer deposition. Tiny frequency dispersion in capacitance measurement and a low Dit value of 5.9 × 1011 cm−2 eV−1 near the midgap confirmed a desirable passivation effect, which was favorable in mitigating the formation of dangling bonds on the Ge surface. A small hysteresis in capacitance was also observed, suggesting that the bulk dielectric was of high quality. On the basis of these characteristics, microwave-activated GeOx is a promising passivation layer material for aggressively scaled Ge-related metal oxide semiconductor devices.In this paper, a method that entails using microwave thermal oxidation to form a high-quality gate dielectric on Ge through surface passivation at considerably low temperatures (<400 °C) is presented. Formation of the GeOx layer was confirmed by x-ray photoelectron spectroscopy. To reduce the bulk trap density and interface trap density (Dit), microwave thermal oxidation was employed for postdeposition microwave thermal oxidation after the deposition of Al2O3 through atomic layer deposition. Tiny frequency dispersion in capacitance measurement and a low Dit value of 5.9 × 1011 cm−2 eV−1 near the midgap confirmed a desirable passivation effect, which was favorable in mitigating the formation of dangling bonds on the Ge surface. A small hysteresis in capacitance was also observed, suggesting that the bulk dielectric was of high quality. On the basis of these characteristics, microwave-activated GeOx is a promising passivation layer material for aggressively scaled Ge-related metal oxide semiconductor devices.

Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium

In this work, we investigated the influence of retrograde-well implantation on hetero-structure body-tied germanium (Ge) FinFET [1]. Using structural engineering, the retrograde well was fabricated prior to Ge epitaxy, which could avoid the activated temperature of dopant in Si substrate. With optimizing the implant condition, the p-Ge/n-Si hetero-structure junction exhibited high I_ON/I_OFF ratio and lower junction leakage (4 × 10^-3 μA/cm²). Furthermore, we also make a comparison of planar and mesa junction structures, mesa junction exhibited lower junction leakage (6× 10^-6 μA/cm²) as compared with the planar one mentioned before, which could be attributed to improvement in peripheral leakage due to dislocation within Ge and Si. Comparing the difference between retrograde-well and implant-free Ge FinFETs, the drain induced barrier lowering (DIBL) was considerably improved by 50 %. Our retrograde-well Ge FinFET exhibited a high I_ON/I_OFF ratio ~ 8×10³ (I_S) than the conventional Ge FinFET (I_ON/I_OFF ~2×10³).

Integration of microwave-annealed oxidation on germanium metal-oxide-semiconductor devices

This work demonstrates high-performance Ge p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) [1] with ternary-phase NiGePt alloy Schottky source/drain (S/D) by low-temperature microwave-activated annealing (MWA) [2]. Process flow of Shcottky junctions is shown in Fig. 1. Interestingly, the formed NiGePt alloy is nearly single crystalline. We found the formation of ternary-phase alloy NiGePt seems very helpful in suppressing the off-leakage of junction, as shown in Fig. 2. The fabricated NiGePt/N-Ge Schottky junction depicted an impressive effective barrier height (ΦBn) of ∼0.59 eV for electrons, leading to a high junction current ratio of >105 at the applied voltage of |Va|= 1 V. Slight increase with increasing deposited Pt thickness can be explained by the improved series resistance, as shown in Fig. 2. The lower process temperature of MWA as compared to the conventional thermal annealing is beneficial for eliminating surface roughness, reducing alloy agglomeration of Schottky contact S/D. As a consequence, we employed the advantages of low-temperature MWA to fabricate the Schottky S/D PMOSFETs. With forming gas annealing, the Ge PMOSFET (L = 4 µm) showed a very high output current of 33.5 µA/µm at VGS−VT= −2.4 and VDS = −2 V. Our ternary Schottky PMOSFET exhibited a high ION/IOFF ratios of ∼ 3.7×103 (ID) and ∼ 1.3×105 (IS), and a moderate subthreshold swing of 126 mV/dec, as shown in Figs. 3.