Chao-Hsin Chien

High-performance nonvolatile HfO/sub 2/ nanocrystal memory

In this letter, we demonstrate high-performance nonvolatile HfO/sub 2/ nanocrystal memory utilizing spinodal phase separation of Hf-silicate thin film by 900/spl deg/C rapid thermal annealing. With this technique, a remarkably high nanocrystal density of as high as 0.9 /spl sim/ 1.9 /spl times/ 10/sup 12/ cm/sup -2/ with an average size <10 nm can be easily achieved. Because HfO/sub 2/ nanocrystals are well embedded inside an SiO/sub 2/-rich matrix and due to their sufficiently deep energy level, we, for the first time, have demonstrated superior characteristics of the nanocrystal memories in terms of a considerably large memory window, high-speed program/erase (P/E) (1 /spl mu/s/0.1 ms), long retention time greater than 10/sup 8/ s for 10% charge loss, and excellent endurance after 10/sup 6/ P/E cycles.

Domain structure study of SrBi2Ta2O9 ferroelectric thin films by scanning capacitance microscopy

Scanning capacitance microscopy was used to image the polarization-induced microstructural patterns of sol-gel derivative SrBi2Ta2O9 (SBT) thin films. A sharp image contrast was induced between the nanosized domains owing to the various polarities, so that the domain structure in the SBT thin film was clearly revealed. As a result, the switched and unswitched regions could be unequivocally identified. This investigation also confirms that the reversal polarization process of a ferroelectric domain is much easier inside a large grain than in a small grain.

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.

Study of thermal stability of nickel monogermanide on single- and polycrystalline germanium substrates

We have investigated the thermal stability of nickel monogermanide (NiGe) films formed by rapid thermal annealing on both single- and polycrystalline Ge substrates. We found that the NiGe phase is the only one present after nickel germanidation in the temperature range 400–700°C. A fairly uniform NiGe film formed on the single-crystalline Ge; it possessed excellent resistivity (15.6μΩcm) and was thermally stable up to 550°C, but it degraded rapidly at higher temperatures as a result of agglomeration. In contrast, the NiGe film formed on the polycrystalline Ge exhibited much poorer thermal stability, possibly because of polycrystalline Ge grain growth, which resulted in columnar NiGe grains interlaced with Ge grains that had a dramatically increased sheet resistance. As a result, we observed that the sheet resistances of NiGe lines subjected to annealing at 500°C depended strongly on the linewidth when this width was comparable with the grain size of the polycrystalline Ge.

Novel two-bit HfO/sub 2/ nanocrystal nonvolatile flash memory

This paper presents a novel nonvolatile poly-Si-oxide-nitride-oxide-silicon-type Flash memory that was fabricated using hafnium oxide (HfO/sub 2/) nanocrystals as the trapping storage layer. The formation of HfO/sub 2/ nanocrystals was confirmed using a number of physical analytical techniques, including energy-dispersive spectroscopy and X-ray photoelectron spectroscopy. These newly developed HfO/sub 2/ nanocrystal memory cells exhibit very little lateral or vertical stored charge migration after 10k program/erase (P/E) cycles. According to the temperature-activated Arrhenius model, we estimate that the activation energy lies within the range 2.1-3.3 eV. These HfO/sub 2/ nanocrystal memories exhibit excellent data retention, endurance, and good reliability, even for the cells subjected to 10 k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile Flash memory applications.

The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with TiN gate electrode

The characteristics of charge trapping during constant voltage stress in an n-type metal–oxide–semiconductor capacitor with HfO2∕SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (ΔVfb) is mainly caused by the trap filling instead of the trap creation [Zafar et al., J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode.

A Study on the Erase and Retention Mechanisms for MONOS, MANOS, and BE-SONOS Non-Volatile Memory Devices

The erase and retention characteristics of MONOS, MANOS and BE-SONOS devices are examined in detail in order to determine their mechanisms. The erase transient current (J) is extracted and plotted against the tunnel oxide electric field (ETUN). Our results show that the erase speed ranking is BE-SONOS > MANOS > MONOS. The difference in erase speed comes from the different erase mechanisms of these devices. The retention characteristics are also compared and discussed.

Characteristics of Atomic-Layer-Deposited Al2O3 High-k Dielectric Films Grown on Ge Substrates

This paper describes the structural and electrical properties of Al 2 O 3 thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300°C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al 2 O 3 film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al 2 O 3 and interfacial GeO 2 appeared at temperatures above 200°C, along with degradation of the GeO 2 /Ge interface. Accordingly, a relatively large gate leakage current (J g ) and a high density of interfacial states D it (>10 13 cm -2 eV -1 ) were observed as a result of deterioration of the entire Al 2 O 3 /Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600°C in a N 2 ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO x volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H 2 /N 2 , 1:10) at low temperature (300°C) improved the capacitance-voltage characteristics of the Pt/Al 2 O 3 /Ge structure, in terms of providing a lower value of D it (ca. 6 X 10 11 cm -2 eV -1 ), a lower value of J g , and a reduced hysteresis width.

Pentacene-based thin-film transistors with multiwalled carbon nanotube source and drain electrodes

In this letter, the authors propose a practical and reliable approach—using deposited multiwalled carbon nanotubes (MWCNTs) as source and drain electrodes—for reducing the contact resistance (Rc) in pentacene-based bottom-contact thin-film transistors. The value of Rc of the devices was closely linked to the resultant length of the deposited MWCNTs; the lowest value was 3×108Ωμm. The largest saturation mobility was 0.14cm2∕Vs; this value reached up to three times higher when the threshold voltage was determined using the maximum transconductance (Gm,max) extrapolation method, rather than the constant current method. The on/off ratio was more than 106.

Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate

In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (les600degC). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (>106 s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory