Cheng-Wen Kuo

White-light emission from InGaN-GaN multiquantum-well light-emitting diodes with Si and Zn codoped active well layer

Si and Zn codoped In/sub x/Ga/sub 1-x/N-GaN multiple-quantum-well (MQW) light-emitting diode (LED) structures were grown by metal-organic vapor phase epitaxy (MOVPE). It was found that we can observe a broad long-wavelength donor-acceptor (D-A) pair related emission at 500 nm/spl sim/560 nm. White light can thus be achieved by the combination of such a long-wavelength D-A pair emission with the InGaN bandedge related blue emission. It was also found that the electroluminescence (EL) spectra of such Si and Zn codoped InGaN-GaN MQW LEDs are very similar to those measured from phosphor-converted white LEDs. That is, we can achieve white light emission without the use of phosphor by properly adjusting the indium composition and the concentrations of the codoped Si and Zn atoms in the active well layers and the amount of injection current.

High brightness InGaN green LEDs with an ITO on n/sup ++/-SPS upper contact

Indium tin oxide (ITO) (260 nm) and Ni (5 nm)/Au (10 nm) films were deposited onto glass substrates, p-GaN layers, n/sup +/-InGaN/GaN short-period-superlattice (SPS), n/sup ++/-SPS and nitride-based green light-emitting diodes (LEDs). It was found that ITO could provide us an extremely high transparency (i.e., 95% at 520 nm). It was also found that the 1.03/spl times/10/sup -3/ /spl Omega/cm/sup 2/ specific contact resistance of ITO on n/sup ++/-SPS was reasonably small. Although the forward voltage of the LED with ITO on n/sup ++/-SPS upper contacts was slightly higher than that of the LED with Ni/Au on n/sup ++/-SPS upper contacts, the 20 mA output power and external quantum efficiency of the former could reach 4.98 mW and 8.2%, respectively, which were much larger than the values observed from the latter. The reliability of ITO on n/sup ++/-SPS upper contacts was also found to be reasonably good.

Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors

The use of low-frequency (1/f) noise to evaluate stress-memorization technique (SMT) induced-stress in n-channel metal-oxide-semiconductor field-effect transistors is investigated. Through observing Hooge’s parameter αH, we found that the unified model can properly interpret the 1/f noise mechanism in our device. On the other hand, lower normalized input-referred noise (LSVG) level in number-fluctuation-dominated regime (region I) and smaller curvature of LSVG versus VGS-VTH in mobility-fluctuation-dominated regime (region II) are attributed to the reduced tunneling attenuation length and Coulomb scattering coefficient, respectively. It represents an intrinsic benefit of 1/f noise behavior stemming from SMT-induced more strain in short channel device.

Origin of Stress Memorization Mechanism in Strained-Si nMOSFETs Using a Low-Cost Stress-Memorization Technique

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (1 0 0) substrate with 〈1 0 0〉channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with L S/D down to 0.11 μm and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

Impact of Ge Content on Flicker Noise Behavior of Strained-SiGe p-Type Metal–Oxide–Semiconductor Field-Effect Transistors

The DC characteristic and low-frequency (1/ f) noise behavior of strained-Si1-xGex p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) with 15 and 30% Ge channel have been investigated and compared with those of Si control counterparts. Enhancement in effective hole mobility of 24 and 45% were obtained in strained-SiGe devices with a 15 and 30% Ge channel, respectively. The strained-SiGe pMOSFETs with a higher Ge buried channel exhibit lower 1/ f noise, indicating that more carriers are confined in the SiGe channel and interface scattering is remote. Moreover, we also found that the Ge concentration plays an important role in the noise mechanism. A new observation shows that carrier number fluctuation is more suitable for interpreting the mechanism of 1/ f noise in strained-SiGe devices with 30% Ge channel, while both number fluctuation noise and mobility fluctuation noise are likely to contribute to the characteristics of SiGe pMOSFETs with 15% Ge and the Si control device.

Enhancement of CMOSFETs Performance by Utilizing SACVD-Based Shallow Trench Isolation for the 40-nm Node and Beyond

This paper reports an improved densification anneal process for sub-atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance CMOSFETs performance for 40-nm node and beyond. The improved STI densification process is demonstrated to generate a lower compressive stress in the active area as compared to the Standard STI process used in 40 nm technology. For nMOS devices with the improved densification process, the reduction of STI compressive stress is beneficial to the electron mobility and leads to an enhancement of on-current (ION ). In addition, the ION enhancements would significantly increase with shrinking the device dimensions (gate width and source/drain length). On the other hand, the improved densification process would not degrade the pMOSFETs performance resulting from the very small piezoresistance coefficients for 〈1 0 0〉 channel direction. The superior junction leakage characteristics for the junction diodes with the improved anneal process can further verify the lower STI-induced compressive stress due to the less energy bandgap narrowing. Hence, the improved STI process can be adopted in 40-nm CMOS technology and beyond, where device structures have very small active areas.

Impact of Reducing Shallow Trench Isolation Mechanical Stress on Active Length for 40 nm n-Type Metal--Oxide--Semiconductor Field-Effect Transistors

We report an improved densification annealing process for sub atmospheric chemical vapor deposition (SACVD)-based shallow trench isolation (STI) to enhance n-type metal–oxide–semiconductor field-effect transistor (nMOSFET) performance for 40 nm node and beyond. Experimental results show that this improved STI densification process leads to lower compressive stress in the small active area compared with the standard STI process. This is beneficial to electron mobility and leads to an enhancement of on-current (ION). Moreover, comparable drain induced barrier lowering (DIBL) and subthreshold swing (SS) characteristics for both devices indicate that the improved densification process would no significant influences on process variations or dopant diffusions. Hence, the improved STI process can be adopted in 40 nm complementary metal–oxide–semiconductor (CMOS) technology and beyond.

Strained-Si nMOSFET with a raised source/drain structure

In this paper, electrical characteristics for strained-Si n-channel metal-oxide-semiconductor field-effect-transistors (nMOSFETs) combining raised source/drain (RSD) structure and cobalt silicide have been studied using the devices with various gate pattern areas (W × L). A strained-Si device with RSD structure provides an additional driving current enhancement (up to 12%) for large-area devices (W × L = 10 × 10 µm2) compared to a strained-Si device without RSD. Further improvement of 24% for device areas down to W × L = 0.15 × 0.15 µm2 indicates that obvious pattern effects exist in strained-Si without RSD case, which is mainly due to the formation of silicide agglomeration at the source/drain (S/D) region and is responsible for the increased S/D resistance.

Low-frequency noise of strained-Si nMOSFETs fabricated on a chemical-mechanical-polished SiGe virtual substrate

The low-frequency noise characteristics in strained-Si nMOSFETs, utilizing the chemical–mechanical-polishing (CMP) treated SiGe virtual substrate have been investigated and compared with the results obtained on strained-Si counterparts without CMP technology. Additional 10.6% mobility improvement and four times lower 1/f noise over 1–100 Hz was obtained for strained-Si devices with the CMP process, indicting that the CMP process provides a smoother surface for the strained-Si/SiGe structure. Moreover, experimental results show that carrier number fluctuation, and not the unified model, is more suitable to interpret the mechanism of 1/f noise in strained-Si devices with the CMP process.

Improved ESD reliability by using a modulation doped Al/sub 0.12/Ga/sub 0.88/N/GaN superlattice in nitride-based LED

Electrostatic discharge (ESD) induced electrical pulse is one of the main reliability concerns of optoelectronic devices. In this paper, a modulation doped Al/sub 0.12/Ga/sub 0.88/N/GaN superlattice are introduced to improve ESD reliability in nitrided-based LEDs. The basic idea of this structure is to spread pulse current when LEDs suffer ESD. The ESD-induced pulse current would be spread laterally in 2D electron gas made by Al/sub 0.12/Ga/sub 0.88/N/GaN heterostructure. Therefore the probability of junction breakdown would be lower.