Cher Liang Cha

Study of copper silicide retardation effects on copper diffusion in silicon

A B-buried layer with a dose of 1×1014 atoms/cm2 was introduced into p-doped Si at a depth of 2.2 μm to enhance copper diffusion via its inherent gettering effect. Copper was then introduced into silicon either via a low-energy implantation followed by a thermal anneal, or through the thermal drive in of physical vapor deposited (PVD) copper film. Secondary ion mass spectrometry depth profiling of both annealed samples later indicated that while substantial amounts of copper was gettered by the B layer in the former sample, no copper was gettered by the B-buried layer in the latter sample. Further analysis with an x-ray diffraction technique showed that copper silicide, Cu3Si was formed in the latter sample. It is thus surmised that the formation of this silicide layer impeded the diffusion of copper towards the B-buried layer. This work investigates the cause of CuSix formation and the underlying reasons for the lower mobility of Cu in PVD Cu film samples.

Effects of deliberate copper contamination from the plating solution on the electrical characteristics of MOSFETs

N-channel and p-channel metal-oxide-semiconductor (MOS) transistors of various (W/L) ratios down to 0.24-/spl mu/m channel length have been used to investigate the effects of deliberate backside copper (Cu) contamination on the MOS field-effect transistor (MOSFET) electrical parameters. The backside of the wafer was flooded with copper sulphate (CuSO/sub 4/) solution and air-dried. High-temperature annealing was carried out to drive Cu into silicon. It was discovered that the backside Cu contamination did not result in any undesirable effects on the MOS device performance. The MOS device parameters such as threshold voltage V/sub TO/, transconductance G/sub m/, drain saturation current I/sub DSAT/, off-current I/sub off/, and junction leakage current for n/sup +//p and p+/n diodes displayed no significant degradation, even after 5 h of annealing at 400/spl deg/C in nitrogen ambient. Secondary ion mass spectroscopy data shows that Cu diffused into silicon only over a short distance, leading to little or no degradation of MOSFETs and junction diodes.

Constant current-stress-induced breakdown of reoxidized nitrided oxide (ONO) in flash memory devices

Flash memory devices, using reoxidized nitrided oxide (ONO) as the interpoly dielectric, have shown rapid degradation in performance under positive and negative constant current- stressing, especially so for the latter case. It is essential and of great urgency to improve the breakdown time (tbd) of the dielectric layer for the application of programming and erasing of flash memory devices. The average dielectric breakdown time of a standard flash test stack, upon a 1 (mu) A positive constant current-stress, is about 50 seconds. Possible causes for the poor performance of the devices under such current stresses, are the rough surface of the bottom polysilicon layer, trapped fluoride ions at the interfaces within the ONO layer and the changes in the occupancy of the interfacial states at the interfaces between the polysilicon layers and the oxides. In this work, we reported the tbds of a type of test stack, that were fabricated in two ways: some tests stacks were defined using the normal (standard) etch process flow (Stack X) while the others had numerous extended overetch (OE) process flow (Stack Z). The latter stacks recorded a higher average tbd value under positive constant current-stressed. Therefore, this work suggested that slight extension of OE duration can be used to improve the tbd of the memory devices under current-stressing.

Plasma etching optimization of oxide/nitride/oxide interpoly dielectric breakdown time in flash memory devices

The breakdown time of flash memory oxide/nitride/oxide (ONO) layer t/sub bd/ under positive constant current stressing has been found to be closely related to the cumulative extent of (over)etch of the tungsten silicide, control polysilicon, and ONO layers, i.e., /spl Sigma/(/spl Lambda/OE). An empirical first-order relation between t/sub bd/ and /spl Sigma/(/spl Lambda/OE) has been derived to facilitate the plasma etch recipe optimization. This has led to a four-fold increase in the average t/sub bd/ across a 200-mm wafer to 208 s. More importantly, the spread in t/sub bd/ has been tightened to /spl sim/5%, which is down from /spl sim/54%.