Ravishankar Sundaresan

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Single-transistor latch in SOI MOSFETs

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported. This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs. The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents. At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage.<<ETX>>

Anomalous subthreshold current&#8212;Voltage characteristics of n-channel SOI MOSFET's

The abnormally high slopes of the subthreshold current-voltage characteristics exhibited by n-channel silicon-on-insulator (SOI) MOSFETs are experimentally related to defect density (off-state leakage current) as well as drain voltage and channel length, and a theoretical physical description of the measured relations is presented and supported. The anomalous subthreshold behavior is attributed analytically to the (floating) body effect due to charging (biasing) by impact ionization at the drain.

Hot-electron degradation of n-channel polysilicon MOSFETs

The stability of the hydrogen passivation in hydrogenated n-channel polysilicon MOSFETs has been studied under thermal stress and hot-electron stress at elevated temperatures. Although the hydrogen passivation is stable at 150 degrees C, channel hot-electron stress at high temperatures appears to create additional grain boundary traps, presumably by breaking the Si-H bonds at the grain boundaries. This mechanism is in addition to the creation of acceptor-type fast interface states that occur in bulk MOSFETs. >

SOI design for competitive CMOS VLSI

Device simulations using a physical SOI MOSFET model implemented in SPICE2 predict that properly designed silicon-on-insulator (SOI) has a substantial advantage over bulk CMOS VLSI with regard to hot-carrier-induced degradation. The simulations show that the (short-) n-channel SOI MOSFET, designed with moderately thin (not ultrathin) film having complete depletion in the film and at the back surface, and without an LDD region, will degrade much more slowly than a contemporary bulk MOSFET with an LDD. This suggests that the 5-V source can be retained for submicrometer SOI CMOS, whereas it must be lowered for bulk CMOS. The simulations and the optimal SOI designs they suggest are supported by measurements of thin-film and bulklike MOSFETs fabricated in SIMOX SOI. >

Modeling of the subthreshold characteristics of SOI MOSFETs with floating body

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current. >

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Measurement and modeling of the sidewall threshold voltage of mesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage. >

Rapid-Thermal Nitridation of SiO2 for Radiation-Hardened MOS Gate Dielectrics

Nitridation of thin SiO2 layers has been achieved by a rapid thermal process in the presence of ammonia. The pre-and post-radiation performances of transistors with nitridated gate insulators have been presented. Nitridation causes a lowering of threshold voltage and channel mobility. Total dose testing indicates that nitridated gate oxides, under certain conditions, produce lower threshold voltage shift as well as less interface state generation than control (oxide) samples.

The characteristics of CMOS devices in oxygen-implanted silicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25*10/sup 18/ cm/sup -2/ to 1.4*10/sup 18/ cm/sup -2/ . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4*10/sup 17/ cm/sup -2/ oxygen dose and annealed at 1150 degrees C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal. >