Chetan Vudadha

CNFET based ternary magnitude comparator

Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper, a ternary magnitude comparator design based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. This design eliminates the usage of complex ternary decoder which is a part of existing designs. Elimination of decoder results in reduction of delay and power. Simulations of proposed and existing designs are done on HSPICE and results proves that the proposed 1-bit comparator consumes 81% less power and shows delay advantage of 41.6% compared to existing design. Further a methodology to extend the 1-bit comparator design to n-bit comparator design is also presented.

Design of Prefix-Based Optimal Reversible Comparator

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bit comparator where two outputs, gi indicating Ai >; Bi and ei indicating Ai = Bi, are generated for ith operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A >; B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate L signal indicating A <; B. The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduced quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2s complement etc. This paper presents an architecture which can perform increment/decrement/2s complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.

A New Design of an N-Bit Reversible Arithmetic Logic Unit

With the advent of nanotechnology, transistors are getting smaller and growing in number according to Moores Law. With this, the issue of heat dissipation is becoming of greater concern to researchers as the transistor heat dissipation reaches the Land Auer limit. Reversible logic is predicted to be an alternative to conventional computing due to lesser energy dissipation and exponentially faster problem-solving capacity. This paper introduces the design of a reversible ripple-carry adder using a mix of the well-known NCV library and the recently introduced NCV-|v1 library, with the assumption of a four-level quantum system. The results for the proposed adder are compared with previous ripple-carry adder designs. It then explores the design of a cost-optimized reversible ALU by modifying the above adder. Finally, a comparison of the proposed ALU is made with one of the latest reversible ALU designs.

Design of CNFET based ternary comparator using grouping logic

This paper presents a design of ternary magnitude comparator based on the CNFET (Carbon Nanotube Field Effect Transistor) ternary logic gates. Ternary logic is a promising alternative to conventional logic design because of its energy efficiency. This energy efficiency is achieved due to the reduced circuit overhead for ternary logic when compared to the conventional binary logic. The comparator design is based on prefix based design and combines ternary and binary logic gates for optimized implementation. The proposed comparator has been implemented and simulated using SPICE. Simulations results indicate that the proposed 1-bit comparator consumes 0.65μW power and has a delay of 21ps. The simulation results for comparators with different operand lengths are also presented.

Energy efficient design of CNFET-based multi-digit ternary adders

Abstract This paper proposes a new technique to implement multi-digit ternary ripple-carry adders in Carbon-nanotube field effect transistor (CNFET) Technology. The proposed multi-digit adder uses efficient half-adders to generate Half-Sum ( H S ) and Half-Carry ( H C ). These half-adder outputs (instead of main inputs) are used to compute carry-out at each digit-adder stage using a delay optimized carry generator. The half-sum and carry-out are then used to compute final sum at each digit-adder stage with the help of a sum generator and low-power encoders. Employing delay optimized carry generator along with low-power encoder results in energy efficient multi-digit ternary adder design. Existing and the proposed multi-digit adders of varied operand sizes are implemented in HSPICE. Simulation results show that the proposed multi-digit adder designs result in up to 52 % reduction in average power consumption and 58 % reduction in Power-Delay Product (PDP), when compared to other multi-digit adders in the literature.

An ESOP Based Cube Decomposition Technique for Reversible Circuits

Reversible logic finds applications in emerging technologies such as quantum computing, optical computing, etc. This has motivated research into development of synthesis and optimization algorithms for reversible circuits. In this paper, a set of rules is presented for the decomposition of a pair of multi-control Toffoli gates (MCT) to reduce the quantum cost of reversible circuits. These rules find pairs of MCT gates, which when decomposed to a network of smaller gates, result in reduced quantum cost. This technique is used in conjunction with an Exclusive-OR Sum-Of-Product (ESOP) based reversible circuit synthesis algorithm to check its efficiency. Results indicate that there is a reduction in quantum cost of several benchmark circuits when compared to the known ESOP based synthesis algorithms.

Optimizing the Reversible Circuits Using Complementary Control Line Transformation

In this paper, a transformation method is presented which converts complementary control lines of a reversible gate pair to equal/similar control lines. A set of optimization rules is discussed that take advantage of the increased equal control lines to reduce the cost. A greedy optimization algorithm, which uses the proposed transformation method and the optimization rules, is presented. Results for a large set of benchmarks confirm that the proposed algorithm performs better when compared with other Exclusive-OR Sum-Of-Product (ESOP) based methods available in the literature.

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders

Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high quantum depth, low quantum cost and/or low garbage outputs and ancilla inputs bits. Secondly design methodology for reversible prefix adders is presented. The reversible prefix adders are characterized by low quantum depth, high quantum cost and/or high garbage outputs and ancilla inputs bits. Finally design of the proposed reversible prefix-ripple hybrid adders is presented and comparison of the different parameters of reversible ripple, prefix and prefix-ripple hybrid adders is illustrated.