Syed Ershad Ahmed

Design of Prefix-Based Optimal Reversible Comparator

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bit comparator where two outputs, gi indicating Ai >; Bi and ei indicating Ai = Bi, are generated for ith operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A >; B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate L signal indicating A <; B. The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduced quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.

A Modified Twin Precision Multiplier with 2D Bypassing Technique

This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs.

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block

An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2s complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay and 50% reduced power delay product. This paper also proposes a reconfigurable INC/DEC/2s complement/Priority encoder circuit which uses the new proposed decision blocks.

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2s complement etc. This paper presents an architecture which can perform increment/decrement/2s complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.

A Unified Architecture for BCD and Binary Adder/Subtractor

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed, keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2s complement and 10s complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing design.

An Iterative Logarithmic Multiplier with Improved Precision

Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic number system results in faster and energy efficient design. In this paper, the authors present a method which combines the Mitchells approximation and hardware truncation scheme in a novel way resulting in an iterative multiplier with improved precision and area. Further, proposed truncation approach and fractional predictor significantly reduce the overall hardware requirement of the multiplier. Experimental results prove the superiority of the proposed multiplier over previous designs.

A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter

This paper presents a new architecture for a 7-bit Binary to BCD (BD) converter which forms the core of our proposed high speed decimal Multi-operand Adder. Our proposed design contains various improvements over existing architectures. These include an improved 7-bit BD Converter that helps in reducing the delay of the Multi-operand decimal Adder. Simulation results indicate that with a marginal increase in area, the proposed BD converter exhibits an improvement of 55% in delay and up to 27% reduction of power-delay product over earlier designs. Further the decimal Multi-operand Adder achieves up to 15% faster design and power-delay product falls to 13% when compared to previously published results.

Improved designs of digit-by-digit decimal multiplier

Abstract Decimal multiplication is a ubiquitous operation which is inherently complex in terms of partial product generation and accumulation. In this paper, the authors propose a generalized design approach and architectural framework for ‘digit-by-digit’ multiplication. Decimal partial products are generated in parallel using fast and area efficient BCD digit multipliers and their reduction is achieved using hybrid multi-operand binary-to-decimal converters. In contrast to most of the previous implementations, which propose changes either in partial product generation or reduction, this work proposes modifications at both partial product generation and reduction stages resulting in an improved performance. A comprehensive analysis of synthesis results (consistent with IEEE-compliant 16-digit decimal multiplier architecture) indicates an improvement in delay of 8–29% and a reduced area-delay product of 4–38% compared to similar work published previously.

A Hybrid Energy Efficient Digital Comparator

Digital comparators are key data path elements for a wide range of applications such as graphics and image processing. Existing designs either consume more power or tend to have large delay. To mitigate these issues, in this brief a new hybrid comparator scheme is proposed, which based on the input operands, selects the most efficient configuration for performing comparison operation. Experimental results show a reduction of 60.6% in delay and 35.8% improvement in power compared to existing schemes.

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits

This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical implementation of constant flagged structures faces. We present the applications of the proposed logic in the exponent biasing circuits of a binary floating-point unit and in a signed-digit decimal adder. Synthesis results show that close to 42% reduction in area and 24% in power is achieved when the unified logic is used with numerically large values like exponent biases. Even for numerically smaller constants like those used in signed-digit decimal adders, we get substantial benefit, with the area reducing by 12.3% and power by 12.4% in this case, thereby demonstrating the effectiveness of the proposed scheme for both small and large constants. Additionally, the propagation delay does not vary by more than 5-6% and power-delay product comes down by almost 20% in both the cases. On account of their power and area efficiency, proposed designs incorporating the unified logic can serve as good frameworks for Embedded DSP and financial applications.