Shih-Wei Lee

Through-silicon-via-based double-side integrated microsystem for neural sensing applications

This paper presents a Through-Silicon-Via (TSV) based double-side integrated microsystem for brain neural sensing applications. Figure 6.3.1 shows the structure of the double-side integrated microsystem. MEMS neural microprobe array and low-power CMOS readout circuit are fabricated on two sides of the same silicon substrate, and TSVs are used to form a low impedance interconnection between the microprobe and CMOS circuitry, thus providing the shortest signal transmission distance from sensors to circuits. The low parasitic impedance of TSV minimizes transmission loss and noise. The overall chip is 5x5mm2, 350μm in thickness including 150μm probe height and 200μm TSV height, respectively. A total of 480 microprobes is divided into 4x4 sensing areas, forming 16channels. 16 TSV arrays are used to connect the microprobe outputs to 16 readout circuits fabricated on the opposite side of the silicon substrate. The proposed structure allows stacking of other CMOS chips onto the circuit side by TSV 3D IC technique.

A TSV-Based Bio-Signal Package With

Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.

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Bio-signal probes that provide stable observation with high-quality signals are crucial for understanding how the brain works and how the neural signal transmits. Because bio-signals are weak and noisy, the length of the string connecting the sensor and Complementary Metal-Oxide-Semiconductor (CMOS) circuit significantly impacts biosignal quality. The collected weak signals from the sensor must pass through a series of interconnections and interfaces that introduce noise and lead to bulky packaged systems. This work uses through-silicon via (TSV) technology to connect the μ-probe array bio-sensor and CMOS circuit located on opposite sides of a chip for brain neural sensing applications. With the elimination of wire bonding and the reduction of the soldering, bio-signal quality can be significantly improved.

-Probe Array

In this research, a novel process scheme for polymer TSV fabrication is proposed to solve the difficulty of polymer liner formation in TSV technology. The corresponding structure shows great manufacturability to replace traditional fabrication approach. In addition, Kelvin structure of the daisy chain is designed for evaluating electrical performance and reliability. Moreover, daisy chain with dummy TSV is designed to verify the impact of TSV pitch on TSV fabrication by using electrical measurement. The reliability tests include thermal cycling and humidity test to verify the quality of proposed polymer TSV design. Finally, a void-free polymer TSV with uniform liner formation is successfully fabricated and demonstrated.

Integrated microprobe array and CMOS MEMS by TSV technology for bio-signal recording application

A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

Polymer TSV fabrication scheme with its electrical and reliability test vehicle

In this research, an optimized process scheme for through glass via (TGV)/through silicon via (TSV) fabrication is proposed to solve the difficulty of copper (Cu) filling in TGV/TSV. Kelvin structure, daisy chain, and comb structure are fabricated for evaluating electrical performance. Comparison between TGV and TSV shows that the power loss and overall process steps (cost) of TGV is lower than TSV for 3D interconnect. Moreover, daisy chain structure at chip-level is fabricated and investigated on its reliability including thermal cycling and humidity test. Finally, TGV/TSV without voids and V-shape pits formed at the filler are successfully fabricated and demonstrated at chip-level with 50-µm TGV/TSV and 200-µm thinned wafers.

A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

A submicron-thick Cu/In bonding by using single sided heating approach has been successfully demonstrated on chip-to-wafer-level without antioxidant metal coating. The single sided heating approach can successfully prevent oxidation of Cu metal on the wafer during bonding. As compared with double sided heating method, a lower specific contact resistance can be obtained in single sided heating method. In addition, post-bonding annealing can further improve the bonding quality. Excellent electrical performances of reliability tests show a great potential for future highly dense interconnect.

Development and electrical investigation of through glass via and through si via in 3D integration

A sealing redistribution layer (RDL) approach for the interposer fabrication is developed to simplify the conventional bottom-up process flow. By using this approach, bottom-up plating can achieve the integration of Cu-filler plating and its bottom RDL simultaneously. In this paper, through-glass via in glass interposer or 3-D integration is fabricated using the proposed approach. The electrical measurement and reliability tests indicate that the proposed approach can be an attractive candidate for interposer fabrication with great performance.

Fine-Feature Cu/In Interconnect Bonding Using Single Sided Heating and Chip-to-Wafer Bonding Technology

A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.

A Novel Sealing Redistribution Layer Approach for Through-Glass via Fabrication

In this research, a single sided heating method is developed to solve the issue of metal oxidation at bottom substrate without antioxidant metal coating in chip-to-wafer bonding. By using optimized bonding parameter, the bonding quality and electrical performance is better than double sided heating in chip-to-wafer bonding. With the help of Cu/In low temperature bonding and single sided heating approach, chip-to-wafer bonding is successfully developed. With the additional annealing process, the bonding duration of single sided heating bonding can be reduced to keep the cost down. Interconnects also maintain good electrical properties after reliability test such as TCT and unbiased HAST. These results prove that the single sided heating method is able to provide good bonding quality and reliability for chip-to-wafer bonding process.