Chiahsun Tseng

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.