Chieh-Ming Lai

The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry (length of diffusion (LOD) and gate width) on the mobility enhancement of lang100rang/(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) were studied in detail. Additionally, the low-frequency characteristics were inspected using low-frequency noise investigation for floating body (FB)-SOI nMOSFETs. Experimental results show that a device with a 1100-Aring HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-Aring; HS CESL due to larger stress-induced defects. The lower plateau of the Lorentzian noise spectrum that was observed from the input-referred voltage noise Svg implies a higher leakage current for devices with a 1100-Aring HS CESL. On the other hand, it was found that devices with narrow gate widths have higher driving capacity for a larger fringing electric field and higher compressive stress in the direction perpendicular to the channel. Because of the more serious impact of compressive stress in a direction parallel to the channel, a device with shorter LOD experiences more serious performance degradation

A deep submicrometer CMOS process compatible high-Q air-gap solenoid inductor with laterally laid structure

A high-quality (Q) on-chip solenoid inductor has been fabricated by 0.18 mm CMOS technology with air-gap structure. The solenoid structure with laterally laid out structure saves the chip area significantly and the air-gap suppresses the parasitic capacitances to obtain high-Q value. Additionally, with software ANSYS simulation, the solenoid inductor also possesses a higher strength for impact (80 000 times) in comparison to a spiral inductor. The measured peak-Q and peak-Q frequency with an air-gap are 8.8 and 1.7 GHz, respectively, which present almost 9% improvements in the magnitude and 54% in the peak-Q frequency in comparison to the conventional solenoid inductor at 8.1 and 1.1 GHz.

Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90-nm nMOSFET

In this letter, mobility improvements by stress contact etch stop layer (CESL) in a strained 90-nm nMOSFET, with and without notched-gate structure, were studied in detail. Compared to the conventional vertical gate, a device with notched gate shows an extra 7% NMOS ION enhancement for the increased stress in the channel region and the less effect of the halo-implanted impurity on channel. Both simulations with TCAD software and measurements confirm that the notched-gate structure efficiently enhances the generation of high tensile stress on the channel region from the CESL and more localized pocket implant

Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs

The hot-carrier-induced degradation of partially depleted silicon-on-insulator complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) at various applied voltages was investigated using 90 nm body-contact silicon-on-insulator (BC-SOI) devices with 1.6 nm gate oxides and various gate widths. In this work, a small gate-width device with a large drain current density was observed to suffer from serious hot-carrier-induced degradation. By inspecting the gate current (IG) degradation, the quality of gate oxide was observed to decay apparently after hot-carrier stressing. For a 90 nm BC-SOI nMOSFET of 1.2 µm narrow gate width, the tolerance of 1.6 nm ultra thin gate oxide layer was very low particularly around the channel edge region; thus, device reliability is very critical and easily degraded because of device gate oxide breakdown after hot-carrier stressing.

Efficient Transistor Optimization with Stress Enhanced Notch-gate Technology for sub-90nm CMOSFET

A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with notch-gate as self-aligned offset spacer possess lower parasitic capacitance and shows extra 7% nMOSFET ION enhancement due to stress CESL more approached to channel center region, enhancing channel carrier mobility efficiently. For pMOSFET, even with inappropriate effect by tensile stress, extra 3% ION enhancement due to optimal channel profile by halo implantation through notch-gate structure.

The Investigation of Post-Annealing-Induced Defects Behavior on 90-nm In Halo nMOSFETs With Low-Frequency Noise and Charge-Pumping Measuring

In this letter, we investigated the effects of post-annealing on indium (In) halo-induced defects for 90-nm nMOSFETs with both low-frequency noise and charge-pumping (CP) current measuring methods. The noise in In halo devices with and without a post-annealing is lower and higher than that in Boron-halo devices, respectively. Additionally, with increase of annealing time, the noise is decreased for the measuring frequency less than 1 kHz due to the efficient elimination of oxide defects. For frequency larger than 1 kHz, the longer annealing time induces a larger quantity interface defects thus enhancing the generation of noise in high frequency. The results are nicely supported by the measurements of gate integrity and CP currents

Stress Technology Impact on Device Performances and Reliability for Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors

In this work, we investigated the thickness effect of a high-stress gate capping layer (GC layer) on 90 nm partially-depleted silicon-on-insulator complementary metal–oxide–semiconductor field-effect transistor (PD-SOI CMOSFETs). Additionally, we inspected the hot-carrier reliability on body-contacted (BC) SOI devices with various thicknesses of the GC layer (1100 and 700 A) and a conventional SiN layer (CN layer). For nMOSFETs, devices with an 1100 A GC layer possess worse characteristics and hot-carrier degradations than devices with a 700 A GC layer in terms of excess high tensile stress. For pMOSFETs, the GC layer only slightly affects device performance, but seriously affects hot-carrier-induced device degradation. Therefore, the thickness of this high-stress GC layer should be optimized to improve the device performance.

The Effect of Mobility Enhanced Technology on Device Characteristic and Reliability for sub-90nm SOI nMOSFETs

For SOI nMOSFET, the impact of high tensile stress contact etching stop (CESL) SiN layer on device performance and reliability were investigated. In this work, device driving capability can be enhanced with thicker CESL layer, larger LOD and narrower gate width. With electrical and body potential inspection, larger STI-induced edge current was found especially in narrow gate device.

Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS ION enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects (Dit) and parasitic capacitances were obtained for the notch-gate samples.

A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the NixSi FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance ION. For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the ION of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data