Che-Hua Hsu

A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs

A “hybrid” high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n⁺poly/SiON@1MV/cm) and low V<inf>TH</inf> (0.25 V) was achieved through optimized HfO<inf>2</inf> high-k, TiN metal and LaO<inf>x</inf> capping layer processes. For PFET, an extra 30% performance improvement and a low V<inf>TH</inf> (0.25V) were achieved by GL process as a result of strain boost and VFB roll-off alleviation [1].

Impacts of Notched-Gate Structure on Contact Etch Stop Layer (CESL) Stressed 90-nm nMOSFET

In this letter, mobility improvements by stress contact etch stop layer (CESL) in a strained 90-nm nMOSFET, with and without notched-gate structure, were studied in detail. Compared to the conventional vertical gate, a device with notched gate shows an extra 7% NMOS ION enhancement for the increased stress in the channel region and the less effect of the halo-implanted impurity on channel. Both simulations with TCAD software and measurements confirm that the notched-gate structure efficiently enhances the generation of high tensile stress on the channel region from the CESL and more localized pocket implant

Reliability Improvement of 28-nm High-

In this letter, performance and reliability of high-k/metal gate MOSFETs can be effectively improved using post metallization annealing. Both oxygen and nitrogen were shown to diffuse into a high-k/SiO2 interfacial layer to suppress the formation of oxygen vacancy, thus reducing the gate leakage current without increasing effective oxide thickness. In particular, with appropriate oxygen annealing, gate-induced drain leakage, drain-current degradation, and gate leakage current variation of high- k/metal gate-last MOSFETs can be efficiently suppressed.

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The impact of aluminum (Al) implantation into TiN/HfO₂/ SiO₂ on the effective work function is investigated. Al implanted through poly-Si cannot attain sufficient flatband voltage (V_FB) shift unless at higher implantation energy. Al implanted through TiN at 1.2 keV with a dose of 5 × 10¹⁵ cm^-2 raised the V_FB to about 250 mV compared with a nonimplanted gate stack. Moreover, the V_FB shift can be up to about 800 mV at 2 keV with the same dose level accompanied with slightly equivalent oxide thickness penalty and gate leakage current degradation. Optimized process window to control Al diffusion depth was essential to minimize these impacts.

/Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices

Effective Work Function Modulation by Aluminum Ion Implantation on Hf-Based High-

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

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The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

/Metal Gate pMOSFET

In this letter, the effect of nitrogen incorporation in a Gd cap layer on the reliability of Hf-based high- k/metal-gate nMOSFETs is investigated in detail. NH3 post plasma treatment was implemented after deposition of the Hf-silicate (HfO2 or HfSiOx) to improve the channel interface state. The Gd cap layer was added on the top of the Hf-based high-k/metal gate for reducing the threshold voltage. However, the nitrogen atoms incorporated in the gate stack via the NH3 plasma treatment could also diffuse into the Gd cap layer, thus blocking the Gd ions at the top of the Hf-based high-k /metal gate, which then generate bulk charges to degrade the devices positive bias instability significantly. We identify the diffusion of nitrogen in the Gd cap layer as well as the location of trap defects in the Hf-based high-k/metal gate with secondary ion mass spectrometry, flicker-noise, and charge-pumping measurements.

Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with notch-gate as self-aligned offset spacer possess lower parasitic capacitance and shows extra 7% nMOSFET ION enhancement due to stress CESL more approached to channel center region, enhancing channel carrier mobility efficiently. For pMOSFET, even with inappropriate effect by tensile stress, extra 3% ION enhancement due to optimal channel profile by halo implantation through notch-gate structure.