Chia-Wei Hsu

Reliability Improvement of 28-nm High-

In this letter, performance and reliability of high-k/metal gate MOSFETs can be effectively improved using post metallization annealing. Both oxygen and nitrogen were shown to diffuse into a high-k/SiO2 interfacial layer to suppress the formation of oxygen vacancy, thus reducing the gate leakage current without increasing effective oxide thickness. In particular, with appropriate oxygen annealing, gate-induced drain leakage, drain-current degradation, and gate leakage current variation of high- k/metal gate-last MOSFETs can be efficiently suppressed.

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The impact of the Si cap/SiGe layer on the Hf-based high-<i>k</i> /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-<i>k</i>/metal gate SiGe pMOSFET can be obtained with an appropriate <i>V</i>_TH (~0.3 V), low <i>C</i> -<i>V</i> hysteresis ( <; 5 mV), and better I_ON - I_OFF , <i>V</i>_TH rolloff, and <i>V</i>_TH stability. By the way, the related interface trap density in the high-<i>k</i> gate stack layer can also be reduced, thus improving the devices NBTI and HCI stressing-induced reliability.

/Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing

The impact of post metal-deposition annealing (PMA) on the trap behavior of high-k/metal-gate metal-oxide-semiconductor field-effect transistors has been studied using drain current random telegraph noise (RTN). The RTN phenomenon is influenced by both trap positions and trap energy, thus corresponding with the PMA passivation mechanism. We found that trap positions in mono-metal-layer annealed (TiN annealed) devices are closer to the TiN/HfO2 interface due to the substitution of nitrogen atoms by oxygen atoms inside the TiN layer. However, replaced nitrogen atoms from TaN can passivate nitrogen defects in TiN that improves device characteristics in dual-metal-layer annealed (TiN/TaN annealed) devices.

The Improvement of High-

In this work, influences of oxygen effect on an Hf-based high-k gate dielectric were investigated. A post deposition annealing (PDA) including oxygen ion after high-k dielectric deposition was used to improve reliability of the Hf-based high-k/metal gate device. The basic electrical characteristics of devices were compared with and without the PDA process. Experiment results show that the oxygen PDA did not degrade the drive current and effective oxide thickness of the Hf-based gate devices. In addition, reliability issues such as positive bias instability, negative bias instability and TDDB were also improved by the oxygen PDA significantly. During the TDDB test, the charge trapping was characterized by an in situ charge pumping system, which could make us to understand the variations of interface trap during the reliability stress easily.

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Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress.

/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

In this letter, the effect of adding ZrO2 to different positions in an HfO2-based high-k (HK) gate-stack is investigated by a low-frequency (1/ f ) noise measurement. The tested nMOSFETs are fabricated using 28-nm gate-last HK/metal-gate technology with a ~ 1-nm SiO2 interfacial layer. The 1/f noise mechanism of these devices is described by the carrier number fluctuation, and the extracted trap densities (Nt)are 8.9 × 1018-5.1 × 1019 eV-1 cm-3. However, reference devices with a pure ZrO2 gate dielectric exhibit 1/f noise characteristics that are consistent with the unified model, which incorporates both the carrier number and the correlated mobility fluctuations. The reference devices are with lower Nt values in the range of 5.8 × 1017-2.4 × 1018 eV-1 cm-3. In addition, there is an increase in Nt as the initial HfO2 layer becomes thicker.These results show that the trapping behavior is mainly dominated by the HfO2 film and is dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2gate-stack.

Impact of oxygen annealing on high-k gate stack defects characterized by random telegraph noise

This paper reports to improve performances of sub-90 nm CMOSFETs with a notch-gate structure enhanced high tensile-stress contact etch stop layer (CESL). Compared to the conventional vertical-gate CMOSFET with an additional offset spacer, the developed structure has the notch-gate as self-aligned offset spacer and lower parasitic capacitance. Beside, the notch-gate shrinks the distance of the CESL to the channel, thus enhances the channel carrier mobility more efficiently. Consequently, an n-MOSFET with this notch-gate structure showed an extra 7% ION enhancement. For p-MOSFETs, even a tensile-stress is not preferable, however, with the structure, an extra 3% ION enhancement was still achieved due to the better channel profile by halo implantation through notch-gate structure.

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing

In this letter, the effect of nitrogen incorporation in a Gd cap layer on the reliability of Hf-based high- k/metal-gate nMOSFETs is investigated in detail. NH3 post plasma treatment was implemented after deposition of the Hf-silicate (HfO2 or HfSiOx) to improve the channel interface state. The Gd cap layer was added on the top of the Hf-based high-k/metal gate for reducing the threshold voltage. However, the nitrogen atoms incorporated in the gate stack via the NH3 plasma treatment could also diffuse into the Gd cap layer, thus blocking the Gd ions at the top of the Hf-based high-k /metal gate, which then generate bulk charges to degrade the devices positive bias instability significantly. We identify the diffusion of nitrogen in the Gd cap layer as well as the location of trap defects in the Hf-based high-k/metal gate with secondary ion mass spectrometry, flicker-noise, and charge-pumping measurements.

NBTI reliability on high-k metal-gate SiGe transistor and circuit performances

Abstract Channel hot-electron-induced degradation on strained MOSFETs is examined experimentally. BSIM stressed model parameters are extracted from measurement and used in Cadence SpectreRF simulation to study the impact of channel hot electron stress on dual-band class-E power amplifier and integrated low-noise amplifier-mixer RF performances. Channel hot electron effect decreases power efficiency of dual-band class-E power amplifier and increases the noise figure of low-noise amplifier-mixer combined circuit.

Low-frequency noise characteristics for various ZrO2-added HfO2-based 28-nm High-k/metal-gate nMOSFETs

A simple and efficient strained engineering was reported, by implementing a notch-gate into high tensile-stress CESL (contact etch stop layer) process. Low process changes were utilized to modulate channel stress and implant profile for generating enhanced performance without any extra process step needed. Compared to conventional vertical-gate CMOSFET with an additional offset spacer, device with notch-gate as self-aligned offset spacer possess lower parasitic capacitance and shows extra 7% nMOSFET ION enhancement due to stress CESL more approached to channel center region, enhancing channel carrier mobility efficiently. For pMOSFET, even with inappropriate effect by tensile stress, extra 3% ION enhancement due to optimal channel profile by halo implantation through notch-gate structure.