Chien-Nan Hsiao

Characteristics of Atomic-Layer-Deposited Al2O3 High-k Dielectric Films Grown on Ge Substrates

This paper describes the structural and electrical properties of Al 2 O 3 thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300°C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al 2 O 3 film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al 2 O 3 and interfacial GeO 2 appeared at temperatures above 200°C, along with degradation of the GeO 2 /Ge interface. Accordingly, a relatively large gate leakage current (J g ) and a high density of interfacial states D it (>10 13 cm -2 eV -1 ) were observed as a result of deterioration of the entire Al 2 O 3 /Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600°C in a N 2 ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO x volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H 2 /N 2 , 1:10) at low temperature (300°C) improved the capacitance-voltage characteristics of the Pt/Al 2 O 3 /Ge structure, in terms of providing a lower value of D it (ca. 6 X 10 11 cm -2 eV -1 ), a lower value of J g , and a reduced hysteresis width.

Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-

In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited- Al₂O₃ gate dielectrics. The magnitudes of the rectifying ratios for the Ge p⁺-n and n⁺-p junctions exceeded three and four orders of magnitude (in the voltage range of plusmn1 V), respectively, with accompanying reverse leakages of ca. 10^-2 and 10^-4 A ldr cm^-2, respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300degC boosted the device on-current, decreased the Al₂O₃/Ge interface states to 8 times 10¹¹ cm^-2 ldr eV^-1, and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm² ldr V^-1 ldr s^-1 and > 10³, respectively, for the p-FET (<i>W</i>/<i>L</i> = 100 mum/4 mum), while these values were less than 100 cm² ldr V^-1 ldr s^-1 and ca. 10³, respectively, for the n-FET (<i>W</i>/<i>L</i> = 100 mum/9 mum). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.

\hbox{Al}_{2}\hbox{O}_{3}

In this study we investigated the interfacial chemistry occurring between an atomic-layer-deposited Al2O3 high-k film and a GaAs substrate and the impact of sulfidization and thermal annealing on the properties of the resultant capacitor. We observed that sulfide passivation of the Al2O3∕GaAs structure improved the effect of Fermi level pinning on the electrical characteristics, thereby providing a higher oxide capacitance, smaller frequency dispersion, and reduced surface states, as well as decreased interfacial charge trapping and gate leakage currents. Photoemission analysis indicated that the (NH4)2S-treated GaAs improved the quality of the as-deposited Al2O3 thin film and preserved the stoichiometry of the dielectric during subsequent high-temperature annealing. This behavior was closely correlated to the diminution of GaAs native oxides and elemental arsenic defects and their unwanted diffusion. In addition, thermal processing under an O2 atmosphere, relative to that under N2, decreased the thicknes...

Gate Dielectric

Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high <i>I</i>_ON/<i>I</i>_OFF ratio (~5×10⁵, at <i>VD</i>=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (<i>V</i>_TH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with <i>L</i>_channel=120 nm and <i>W</i>_Fin=40 nm. Multifin Ge FinFET with <i>L</i>_channel=170 nm and <i>W</i>_Fin=50 nm is also illustrated. Both <i>N</i>- and <i>P</i>-FinFETs possess high <i>I</i>_ON/<i>I</i>_OFF ratio over 10⁴. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.

Effects of interfacial sulfidization and thermal annealing on the electrical properties of an atomic-layer-deposited Al2O3 gate dielectric on GaAs substrate

The authors present a linear-regression method based on a five-element circuit model to correct measured capacitance-voltage and conductance-voltage curves. This model explains the effects of series resistance and parasitic capacitance/inductance on the frequency dispersion of measured capacitance and the magnification of measured conductance. These extracted parasitic components show significant dependencies on the geometry of capacitor structure, thereby causing different frequency-dependent capacitance characteristics in measurements.

Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High

In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance <i>G</i>_sub and high-low transition frequency <i>f</i>_tran, to explore the differences in the minority-carrier response. The Arrhenius-dependent <i>G</i>_sub characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of <i>f</i>_tran. We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency <i>C</i>- <i>V</i> curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al₂O₃/Ge MOS capacitors were consistent with the values of <i>G</i>_sub and <i>f</i>_tran obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the <i>G</i>_sub/<i>f</i> conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. ( 2-4) &times;10¹⁵ cm^-3 exist in present-day low-doped Ge wafers.

{\rm I}_{\rm ON}/{\rm I}_{\rm OFF}

This paper has studied the electrical and interfacial properties of atomic-layer-deposited Al2O3 thin film on ammonium-sulfide passivated GaAs. It was found that the Al2O3 deposited at 300°C relative to that at 100°C showed the nearly four orders of magnitude reduction in gate leakage current at the capacitance-equivalent-thickness of 40 A. The capacitance–voltage (C-V) characteristics displayed the higher oxide capacitance, reduced frequency dispersion and less charge trapping when GaAs receiving (NH4)2S sulfide immersion; these improvements can be reasonably explained by the suppression of both native oxides and the resultant improved interface quality. Annealing as-deposited Al2O3/GaAs structures at high temperatures further reduces the Fermi level pinning effect on accumulation capacitance, however, causes an increase in C-V frequency dispersion and gate leakage current. We suggested that these phenomena are strongly associated to the amount of As-related defects resided at the dielectric/substrate interface during thermal desorption.