Chien-Nan Liao

High performance power VDMOSFETs with a split-gate floating np-well design

Low gate charge power vertical double-diffused MOSFET devices are required for high-frequency systems. In this study, we proposed a split-gate with a floating np-well structure, which realizes a low gate charge performance without significantly degrading the breakdown voltage. The proposed structure removes the partial gate area between the gate and drain overlap area, and combines with an additional np-well. By this approach, the gate charge and switching loss can be reduced, and the breakdown voltage can be sustained. The gate–drain charge and gate charge of the split-gate with an np-well structure are 41.4% and 66.1% of the conventional device, respectively. These improvements are beneficial for reducing the switching loss of the devices.

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.

Potential and Electric Field Distribution Analysis of Field Limiting Ring and Field Plate by Device Simulator

Potential and strength of surface electric field distribution have strongly influence on breakdown voltage and reliability of power semiconductor devices. Potential distribution can be determined by different field-limiting ring and field plate design which can be described by solving Poissons equation in one dimension briefly. In this paper, the influence of design factors such as spacing between main junction and ring, ring width, and field plate width on potential and strength of surface electric field distribution are analyzed. From the simulation results, the relationship between those factors and potential and strength of surface electric field distribution can be found. Understanding the effect of design factors upon the junction termination edge, multi field-limiting rings and field plates of high breakdown power devices can be designed.

A Novel Self-Aligned Raised Source/Drain Polysilicon Thin-Film Transistor With a High-Current Structure

In this letter, a high-current self-aligned raised source/drain polycrystalline silicon thin-film transistor (HCSARSD-TFT) is proposed and demonstrated for the first time. This new self-aligned device features two channels, i.e., a nitride spacer offset-gated structure and a raised source/drain (RSD) region, that reveal better device performance. Our experimental results show that the on-current of the HCSARSD-TFT is about two times higher than that of the conventional structure, and the leakage current is considerably reduced simultaneously. In addition, since the gate and RSD areas of the proposed device are self-aligned, no extra mask is needed when comparing it with conventional coplanar RSD TFTs.

A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

In this letter, a novel double-channel polycrystalline-silicon (poly-Si) thin-film transistor (DCTFT) is proposed and demonstrated. The DCTFT, which includes two channels with a thicker source/drain (S/D) region, a field-induced drain, and an offset structure, reveals better device performance and lower S/D resistance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability such as the threshold-voltage shift under a high gate bias is also improved by this two-channel and thick-S/D-region structure design. The lower drain electric field of the DCTFT is also a benefit to the device scaling down for better performances.

Comparison of termination structure design by device simulator

Termination region plays an important role in high voltage power VDMOSFETs. Termination structure such as floating-field-limiting-rings and field plates are the common structures used in a termination region because they can be fabricated without additional masks. However, sometimes we use both of them, sometimes only the floating-field-limiting-ring. The difference between these structures must be known while designing. In this paper, we compare and discuss the difference of the floating-field-limiting-rings with and without field plates. Understanding the difference is helpful for designing and saving time.

High voltage power MOSFET with reduced JFET area design

A high voltage power vertical double-diffused MOSFET with reduced JFET area by using an overall implantation was discussed. The reduced JFET area realizes a low gate charge and a high switching speed, due to the reduction of the gate-drain overlapped area. The measured gate-drain charge and gate charge can be improved by 61.1% and 71.8 %, respectively. The F.O.M of the proposed device and the conventional one is 64.4 nΩ×C and 190.9 nΩ×C, respectively. We also discussed the reliability issue and compared the avalanche capability to the proposed structure and the conventional device. The ruggedness of the proposed devices can be improved by a higher cell density design with a planar oxide self align p+ implantation process.

Device linearity improvement of In0.49Ga0.51P/In0.15Ga0.85As doped-channel FETs with a metal plug alloy process

The effect of reducing source and drain resistance on the device linearity of doped-channel heterostructure FETs is investigated in this work. The proposed metal plug alloy process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer, which not only enhances the device source resistances, dc, RF and power characteristics, but also improves the device linearity of doped-channel heterostructute FETs. In particular, we compare the performance of dc, RF and microwave power characteristics between proposed partial drain/source ohmic recess metal plug anneal InGaP/InGaAs/GaAs doped-channel FETs (OR-DCFETs) and conventional doped-channel FETs (DCFETs). Due to lower source and drain resistances, OR-DCFETs demonstrate higher device current, higher power-added efficiency (PAE) and especially better device linearity than conventional doped-channel FETs, making OR-DCFETs very suitable for microwave power device applications.

Computer‐aided evolution for solving the analytic Kronig‐Penny model

Abstract The Kronig‐Penney model consists of a periodic potential function, which is used to derive the concepts of allowed and forbidden energy bands. Here, to circumvent the tedious evolution, it is helpful to use computer methods to derive the textbook equation of the analytic Kronig‐Penney model. The hierarchical methodology with the shorter symbols can effectively reduce the complication in the expression of the 4 × 4 matrix. By defining the symbol sequence, we can easily reduce terms by cancellation. With these methods and computer‐aided evolution, we can derive the Kronig‐Penney model from the matrix expression to the textbook form without the extremely laborious evolution.

Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors

An antimony (Sb)-doped substrate is used to fabricate high voltage power metal oxide semiconductor field effect transistor (MOSFET) to prevent out-doping phenomenon. Since the contact resistance of Sb-doped substrate is higher than that of the phosphorus (P) and arsenic (As)-doped substrates, which are widely used for low breakdown voltage power MOSFETs, devices that are fabricated with an Sb substrate have a higher source–drain forward voltage (VSD). The increased VSD is associated with power loss while the device is under switching in an inductive load bridge circuit. In this work, devices were baked at different temperatures for various times to reduce the VSD. The VSD was efficiently reduced at 300 °C after 6 h baking.