Yao-Tsung Tsai

An efficient analytical model for calculating trapped charge in amorphous silicon

We present an efficient analytical model for calculating the trapped-charge density as a function of Fermi energy based on two exponential regions for density-of-states distribution in hydrogenated amorphous silicon. In this efficient model, the trapped-charge density is calculated without numerical integration and without curve fitting as a function of Fermi energy. Comparisons between the analytical and the numerical models have been made and excellent agreement has been obtained. Such a model is useful as an aid to study the impact on the performance of amorphous-silicon devices such as thin-film transistors. >

Levelized incomplete LU method and its application to semiconductor device simulation

Abstract In circuit simulation, the CPU time is spent in two parts: one is to transfer the circuit equation into the corresponding linear equation Ax = B , the other is to solve this matrix equation. In order to improve the simulation speed and apply our method to mixed-level device and circuit simulation, we propose to simplify the creation of the matrix equation by equivalent subcircuit, and speed up the simulation by levelized incomplete LU factorization [Karl-Michael E, Walter LE. IEEE Trans Comp Aided Des Integ Circ and Sys 1995;14:720.]. The levelized incomplete LU is used to solve Ax = B because it offers, the good convergence of the direct method and the high speed, small memory space of the iteration method. The Ax = B is obtained by transferring the Poisson equation and continuity equation into their equivalent circuits [Leblebici Y, Unlu MS, Morkoc H, Kang SM. IEEE Int Symp Circ and Sys 1992;2:895; 1995;13:396.] to simplify the mixed-level simulation. Finally, we will apply the above methods to the simulation of PN diodes and verify their performance on the simulation and design of semiconductor devices.

An improved levelized incomplete Lu method and its application to 2d semiconductor device simulation

Abstract Numerical simulation of semiconductor devices plays a very important role in the design and development of integrated circuits. We will present a new circuit simulator with an improved Levelized Incomplete LU method to perform such simulations. To have an environment for evaluating the interaction between a semiconductor device and a circuit, we use the equivalent circuit approach. This approach allows for simple representation carrier transport models of devices through equivalent circuit elements such as voltage controlled current sources and capacitors. Therefore, we can perform mixed‐level simulation in general circuit simulators. We will take a PN diode switching circuit and MOSFET as examples to test our equivalent circuit model and the improved circuit simulator. The comparison between improved matrix solution method and the conventional method will be demonstrated too. We will also show our method yields better matrix solutions than conventional methods

High performance power VDMOSFETs with a split-gate floating np-well design

Low gate charge power vertical double-diffused MOSFET devices are required for high-frequency systems. In this study, we proposed a split-gate with a floating np-well structure, which realizes a low gate charge performance without significantly degrading the breakdown voltage. The proposed structure removes the partial gate area between the gate and drain overlap area, and combines with an additional np-well. By this approach, the gate charge and switching loss can be reduced, and the breakdown voltage can be sustained. The gate–drain charge and gate charge of the split-gate with an np-well structure are 41.4% and 66.1% of the conventional device, respectively. These improvements are beneficial for reducing the switching loss of the devices.

High-Performance Double-Channel Poly-Silicon Thin-Film Transistor With Raised Drain and Reduced Drain Electric Field Structures

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.

Potential and Electric Field Distribution Analysis of Field Limiting Ring and Field Plate by Device Simulator

Potential and strength of surface electric field distribution have strongly influence on breakdown voltage and reliability of power semiconductor devices. Potential distribution can be determined by different field-limiting ring and field plate design which can be described by solving Poissons equation in one dimension briefly. In this paper, the influence of design factors such as spacing between main junction and ring, ring width, and field plate width on potential and strength of surface electric field distribution are analyzed. From the simulation results, the relationship between those factors and potential and strength of surface electric field distribution can be found. Understanding the effect of design factors upon the junction termination edge, multi field-limiting rings and field plates of high breakdown power devices can be designed.

A Novel Self-Aligned Raised Source/Drain Polysilicon Thin-Film Transistor With a High-Current Structure

In this letter, a high-current self-aligned raised source/drain polycrystalline silicon thin-film transistor (HCSARSD-TFT) is proposed and demonstrated for the first time. This new self-aligned device features two channels, i.e., a nitride spacer offset-gated structure and a raised source/drain (RSD) region, that reveal better device performance. Our experimental results show that the on-current of the HCSARSD-TFT is about two times higher than that of the conventional structure, and the leakage current is considerably reduced simultaneously. In addition, since the gate and RSD areas of the proposed device are self-aligned, no extra mask is needed when comparing it with conventional coplanar RSD TFTs.

An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer

An analytical model is presented to determine the potential and electric field distribution along the semiconductor surface of new silicon-on-insulator (SOI) reduced surface field (RESURF) device. The SOI structure is characterized by a semi-insulating polycrystalline silicon (SIPOS) layer inserted between a silicon layer and a buried oxide. An improvement in the breakdown voltage due to the presence of the SIPOS shielding layer is demonstrated. Numerical simulations using medici are shown to support the analytical model.

A Novel High-Performance Poly-Silicon Thin-Film Transistor With a Double-Channel Structure

In this letter, a novel double-channel polycrystalline-silicon (poly-Si) thin-film transistor (DCTFT) is proposed and demonstrated. The DCTFT, which includes two channels with a thicker source/drain (S/D) region, a field-induced drain, and an offset structure, reveals better device performance and lower S/D resistance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability such as the threshold-voltage shift under a high gate bias is also improved by this two-channel and thick-S/D-region structure design. The lower drain electric field of the DCTFT is also a benefit to the device scaling down for better performances.

An Efficient Trapped-Charge Calculation in amorphous Silicon for Device Simulation

We present an efficient analytical model for calculating the trapped-charge density as a function of Fermi energy based on two exponential regions for density-of-states distribution in hydrogenated amorphous silicon. in this efficient model, the trappedcharge density is calculated without numerical integration and without curve fitting as a function of Fermi energy. Comparisons between the analytical and the numerical models have been made and excellent agreement has been obtained. Such a model is useful as an aid to study the impact on the performance of amorphous-silicon devices such as thin-film transistors. SUMMARY Amorphous silicon (a-Si) thin-film transistors (TFT) are finding applications for Iargearea integrated circuits in flat liquid-crystal displays, solid state imager, electronic copiers, printers, and scanners. Device simulation [l] has been used to investigate the performance of a-Si TFT. The major difference between a-Si and single crystalline silicon is the large localized states in mobility gap. To simulate device performance, one needs to accurately include the trapped charge into Poisson’s equation. In general, trapped charge is calculated by integrating the product of the Fermi-Dirac occupation function and the localized density of states (DOS). This calculation requires a numerical integration and will cause problem in two- or three-dimensional device simulation due to the large amount computer time for numerical integration. In this paper, we presents an efficient analytical model for calculating trapped-charge density as a function of Fermi energy based on two exponential regions for DOS distribution in hydrogenated amorphous silicon. If we change the magnitude and slope of DOS distribution, there is no need to modify this model. The localized states may be characterized by an two exponential regions for the tail states and the deep states which has been confirmed by experimental data published in [2]. Analytic expressions for the density of trap states can be cypressed by