Chih-Hsing Lin

A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications

In this paper, a wide-range DLL-based frequency multiplier with PMOS active load for communication applications is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. The DLL-based frequency multiplier uses simple exclusive-or (XOR) gates and phase blending technique for the frequency multiplications. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the VCDL is even. The output frequency of the proposed frequency multiplier ranges from 80MHz to 2.24GHz using TSMC 0.18mum CMOS process. The locked time is 0.96ns locked time at 400MHz. The peak-to-peak jitter is 46ps at 80MHz and 95.3ps at 2.24GHz. The power consumption of proposed frequency multiplier is 25.79mW at 400MHz.

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13μm CMOS technology

In this paper, we present a 7 Gbps/Ch quad SerDes integrated with a 4times4 load-balanced switch fabric circuit for high speed networking applications. To achieve high-speed and low area, we propose an area-saving RF model device for the SerDes design. The area-saving RF model has almost the same speed and jitter performance with the RF model but only consumes one half of the area. In our hybrid design of the SerDes architecture, the area-saving RF model mixed with the baseband model can reduce 75% of area compared with the design using only the conventional RF model. The grounded coplanar waveguide (GCPW) type transmission line is also employed to reduce the clock tree skew for the quad SerDes to within 1 ps. The total area is 3 mm times 2.48 mm, including the switch fabric, the quad SerDes interface, and a LC-PLL. In our results, each input/output port of the 4x4 switch fabric can achieve 7 Gbps data rate, and the overall throughout is 28 Gbps.

A real-time bridge structural health monitoring device using cost-effective one-axis accelerometers

This work demonstrates a real-time bridge structure health monitoring device (HMD) with using three 1-axis accelerometers, Gateway, and analog to digital converter (ADC). The proposed HMD achieves the features of low cost and data synchronization of three 1-axis accelerometers. Furthermore, we develop a packet acquisition program to receive the data from remote sensors and then classify it based on time and date. Compared with 3-axis accelerometer, our proposed 1-axis accelerometers based device achieves 59.59% cost saving with high sensitivity 2000 mV/g.

A novel design flow for a 3D heterogeneous system prototyping platform

This paper presents a novel design flow for three-dimensional (3D) heterogeneous system prototyping platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. Based on system partition and tri-state interface connecting, the MorPACK system can be efficiently extended by system bus interfaces and can improve the functions by only updating the bare die/module. In addition, the total silicon prototyping cost of heterogeneous SoC projects can be greatly reduced by sharing the MorPACK common system platform. To demonstrate the effectiveness of the proposed platform, six SoC projects are implemented. The results show that there are 79.13% fabrication cost reduced by the MorPACK platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited.

A modularized 3D heterogeneous system integration platform

This paper proposes a modularized three-dimensional (3D) heterogeneous system integration platform architecture, namely, MorPACK (morphing package). The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. An efficient reconfiguration is enabled thanks to the use of system bus interfaces and exchange the bare die/module by system dividing and tri-state interface connecting. Six SoC projects/designs are implemented to demonstrate the effectiveness of the proposed MorPACK platform. The average silicon area of each project is about 122.59 mm2 using the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 587.44 mm2 obtained by implementing these projects separately, the results show that there are 79.13% fabrication cost reduced by the MorPACK platform. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

A cost effective three-axis accelerometer for building structure health monitoring

To ensure critical structures safety operation, the building structure monitoring system is needed. The accelerometers and temperature sensors are usually used to achieve reliable inspection of structures. The main goal of this work is the realization of a customized building structure health monitoring, based on three 1-axis accelerometers, Gateway, analog to digital converter (ADC), and data logger. The proposed Building Structure Health Monitoring Device (BSHMD) achieves the features of low cost by using three 1-axis accelerometers with the data synchronization problem being solved, and easily installation and removal. Furthermore, we develop a packet acquisition program to receive the sensed data and then classify it based on IP address, time, and date. Compared with 3-axis accelerometer, our proposed 1-axis accelerometers based device achieves 64.3% cost saving. Compared with previous structural monitoring device, the BSHMD achieves 89% area saving. Therefore, with using the proposed device, the real-time diagnosis system for building damage monitoring can be conducted effectively.

Structural health monitoring of bridges using cost-effective 1-axis accelerometers

This paper proposes a structure health monitoring device (HMD) with using three 1-axis accelerometers, microprocessor, analog to digital converter (ADC), and data logger for long span bridge. The proposed monitoring system achieves the features of low cost and data synchronization of three 1-axis accelerometers. Furthermore, we develop a packet acquisition program to receive the sensed data and then classify it based on time and date. Compared with 3-axis accelerometer, our proposed 1-axis accelerometers based device achieves 64.3% cost saving. Besides, the optimal sensor number can be verified by our proposed equation with only 0.37% error in terms of sample rate. Therefore, with using the proposed device, the real-time diagnosis system for bridge damage monitoring can be conducted effectively.

Morpack Cube: A portable 3D heterogeneous system integration platform

This paper proposes a portable three-dimensional (3D) heterogeneous system integration platform with reusable sockets, namely, morphing package Cube (MorPACK Cube). The architecture of MorPACK Cube platform achieves the features of miniaturization and portability without a carrier board. Our proposed MorPACK Cube integrates accelerometer sensor, gyroscope sensor and electronic compasses sensor and then exhibits on Andriod platform through Bluetooth wireless communication. Furthermore, we develop an Mobile APP, namely SigView, to display and analysis the collected data from these sensors. The proposed MorPACK Cube is used for sensor applications to demonstrate the effectiveness, compared with the total area 434cm2 obtained by implementing MorPACK Cube platform with a carrier board, the results show that there are 91.14% area cost reduced by the MorPACK Cube platform without a carrier board. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.

Boundary scan test solution for MorPACK platform

This paper presents a boundary scan test solution for three-dimensional (3D) heterogeneous system integration platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. In order to verify the function of MorPACK platform, the interconnection wire is a critical component between circuit modules and connection modules on PCB board. The boundary scan test is used to check the correctness of interconnection wire on PCB board and then achieves high fault coverage and high quality. The simulation results show that the proposed boundary scan test solution is slightly increased in area and timing of ARM CPU with 1.4% and 1.9% respectively. The south-bridge only consumes the area plenty with 4.5%. Therefore, the proposed method can arrange the routing of PCB board to achieve the verification of interconnection wire and then obtains the small area cost without addressable scan port chip.

Microphone array application prototyping with MorPACK heterogeneous integrated system

This paper proposes a heterogeneous system platform to speed up the implementation and verification of innovative design for integrating microphone array application. Comparing to state-of-the-art prototyping systems, the proposed platform named MorPACK (morphing package) achieves modularity and flexibility by adopting three concepts: substrate-level modularization, three-dimensional (3D) module stack, and components reuse. In addition, we also provide the MorPACK platform which helps designers to concentrate their efforts on their own functional module(s), and easily reuse existing modules like playing bricks, which greatly reduce the development cycle of an embedded system. The implementation results show that there are 79.13% fabrication cost reduced by the MorPACK common platform in TSMC 90nm CMOS. Besides, around 60% performance improvement of operation frequency can be benefited. We adopt the microphone array cooperated with MorPACK to enhance the design flow arrangement. Furthermore, this application can be used as a reference design for distinct applications.