Rajeeva Lahri

Poly emitter bipolar hot carrier effects in an advanced BiCMOS technology

Hot carrier effects due to reverse biasing of emitter-base junction in a poly emitter bipolar transistor are discussed. Degradation of transistor current gain under DC, pulsed DC and AC stress conditions is found to be determined by the total injected charge through the reverse biased junction. These results coupled with the design simulations are used to predict the reliability of bipolar devices in a BiCMOS circuit.

Transient substrate current effects on n-channel MOSFET device lifetime

The n-channel MOSFET transient substrate current during dynamic hot-carrier stressing has been found to be a strong function of the rise and fall time of the gate/drain voltages. At fast rise and fall times (<10 ns), the displacement current associated with the dynamic stressing becomes a significant portion of the transient substrate current. The magnitude and direction of displacement current significantly affects the extent of the device degradation. The nature of the transient substrate current and its effect on MOSFET device lifetime is demonstrated here. Device degradation is found to depend on the circuit environment in terms of bias conditions. Therefore, performance degradation due to hot carriers is also dependent on the application of the MOSFET in the circuit. A BiCMOS 15-ns 256 K SRAM (static random access memory) is used to demonstrate this methodology.<<ETX>>

Mismatch drift: a reliability issue for analog MOS circuits

Mismatch drift is a major process reliability issue for analog and mixed-signal designs. Mismatch stability was examined for a 0.8- mu m CMOS process using a cascode current minor test circuit. After 1000-h burn-in at 125 degrees C under matched gate voltage stress, no drift in parameter matching was measured. However, for the same burn-in conditions with unmatched gate voltage stress, drifts in threshold voltage mismatch of 0.3 mV for n-channel and 2.4 mV for p-channel transistor pairs have been observed. This mismatch drift is larger for short-channel devices, indicating that the drift-causing phenomenon is greater at the drain/source edge.<<ETX>>

0.6 amu;m, single poly advanced BiCMOS (ABiC IV) technology for ASIC applications

An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition to silicided poly for local interconnection, this technology offers four layers of metallization with chemical vapor deposition (CVD) tungsten-filled contacts and vias. Interconnection delays are 1 ps/mil. ABiC technology is most attractive for high-performance 50K to 100K gate ECL logic arrays, 100K to 200K gate CMOS/BiCMOS logic arrays, and high-density ASIC products requiring embedded memories

Submicron Large-Angle-Tilt Implanted Drain technology for mixed-signal applications

This paper reports the use of LATID in submicron MOS technology to improve both analog and digital device performance and reliability. It is demonstrated that LATID technology not only improves device reliability, but also significantly improves output resistance and voltage gain. A submicron CMOS technology optimized for mixed-signal applications based on a conventional CMOS process has been fabricated without compromising digital performance or increasing process complexity.<<ETX>>

Ion beam shadowing effect in submicrometer large-angle-tilt implanted drain (LATID) MOSFETs

Abstract An orientation-dependent device characteristic in LATID MOSFETs is reported. By controlled device fabrication splits, it is confirmed that the orientation-dependent device characteristics are caused by the large-angle-tilt (LAT) implant which creates n − drain regions with different lengths and doping concentrations due to poly gate shadowing effect. These differences in n − region cause transistor performance and reliability, such as saturation current and hot-carrier injection, to vary significantly with respect to transistor orientation.

A 0.8 mu m advanced single poly BiCMOS technology for high density and high performance applications

A single poly, 0.8 mu m BiCMOS technology having both high-performance CMOS and 14 GHz ASPECT III n-p-n transistors is described. The advanced features of this BiCMOS technology include a low encroachment, defect-free recessed oxide isolation process, self-aligned integrated well taps for MOS devices, double diffused bipolar process, silicided local interconnect, and four levels of metallization with tungsten plugs. Ring oscillator gate delays of <150 ps BiCMOS, <90 ps CMOS, and<50 ps ECL are obtained with this process. This technology is most applicable to high-performance/high-density standard cell ECL gate array circuits requiring embedded memory.<<ETX>>

Improving hot-electron reliability through circuit analysis and design

On-chip hot-electron test/stress structures have been developed. These structures provide insight into device degradation under real circuit operation. This makes it possible to accurately predict device lifetime in a specific circuit application. A methodology leading to novel hot-electron design guidelines is proposed based on the device operating conditions and its susceptibility to hot-electron effects. By following these guidelines, circuit reliability can be improved without adversely affecting circuits performance. The correlation between device and circuit degradation has been obtained through subcircuit analysis and simulation. As a result, hot-electron circuit lifetime can be used as one of the design parameters to insure long term reliability of the circuit. An example of reliability through design is given.<<ETX>>

A 2.5 ns ECL 16*16 multiplier

A 16*16 b integer multiplier is described that has achieved a measured delay of less than 2.5 ns, register to register, for a full 16*16 multiply. It was fabricated using ASPECT 3, a 0.8 mu m bipolar process with silicided polysilicon and four-level metallization. A standard cell methodology using an automated sizing and scaling approach was used. In register-to-register mode the worst case clock period is 2.495 ns, with a measured pin-to-pin flow thru mode latency time of 3.37 ns. The I/O delay plus register setup is 875 ps.<<ETX>>

Gate oxide charge-to-breakdown correlation to MOSFET hot-electron degradation

Substrate current by itself is found not to be a sufficient indicator of degradation. Experiments using active-area test capacitors with and without poly edges confirm that the gate-oxide trap density beneath the poly edges is equally important in determining the degradation. Certain processing steps have been identified as being responsible for gate-oxide degradation. An optimization of these steps has resulted in improved hot-electron degradation behavior.<<ETX>>