Chih-Tang Peng

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

The demands for electronic packages with lower profile, lighter weight, and higher input/ output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent demand high I/O density and good reliability characteristics have led to the evolution of ultra high-density non-solder interconnection, such as wire interconnect technology (WIT). New technology, which uses copper posts to replace the solder bumps as interconnections, has improved reliability. Moreover, this type of wafer level package produces higher I/O density, as well as ultra fine pitch. This research focuses on the reliability analysis, material selection and structural design of WIT packaging. This research employs finite element method (FEM) to analyze the physical behavior of packaging structures under thermal cycling conditions to compare the reliability characteristics of conventional wafer level and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature-dependent material properties will be applied to all models. @DOI: 10.1115/1.1481368#

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput.

Design, fabrication and comparison of lead-free/eutectic solder joint reliability of flip chip package

This investigation presents a detailed design procedure for a lead-free flip chip BGA package which includes solder bump profile prediction, FEM simulation, test vehicle design/fabrication and accelerated thermal cycle (ATC) testing to study the reliability issues of the flip chip packages. The solder joint reliability of a flip chip package depends on the solder materials and the solder geometry. Therefore, this study is divided into two main topics: one is the effect of solder joint material (eutectic 63Sn/37Pb solder and lead-free 96.5Sn/3.5Ag solder) on the solder joint reliability, and the other is the effect of the geometry on the Sn/Ag solder joint reliability. The trends of the ATC testing coincide with the FE analysis results, thus confirming that this analysis-fabrication procedure is feasible for the solder joint geometry and material design of a flip chip BGA package.

Failure life prediction and factorial design of lead‐free flip chip package

Abstract As is well known, the design parameters of the packaging material and structure greatly influence the reliability of the packaging. When it comes to flip chip packages, the package reliability design becomes more complicated. In addition, the interactions between these different design parameters remain unclear, especially for lead‐free solder applications. Based on the above, FEM factorial analysis was employed in this study to investigate the interrelationship of the design parameters. A factorial analysis with two levels and five factors was chosen. The factors included pre‐solder thickness, thickness of the BT core in the laminate substrate, bumping height, substrate side pad opening, and the climbing height of the underfill. The factorial design method was repeated twice with two kinds of solder bump materials (63Sn/37Pb and 96.5Sn/3.5Ag). The findings show that the structures with the larger BT core thickness, thicker pre‐solder layer and higher bump height have the better solder bump reliability. In terms of the factorial analysis, the BT core thickness was the factor having the most influence on reliability. The interactions between the factors were observed in this study.

Local-strain effects in Si∕SiGe∕Si islands on oxide

The tensile-strained Si, based on the misfit between Si and SiGe gives high speed and high drive current to the metal-oxide-silicon field effect transistors. In order to achieve the total system minimum energy, the island edge, within some characteristic length, bends upwards giving rise to a distorted lattice, as simulated by the finite element method. The finding indicates that the conventional strain partition rule of Si∕SiGe∕Si layers used for a large island size (>10μm) is not adequate for a small island size (<200nm) due to the significant local-strain effect of the edge lattice distortion. For a small island size, the bending from the edge can significantly affect the strain on the surface of the top Si layer, and a compressive strain or reduced tensile strain occurs at the center of the top Si layer, while the conventional strain partition rule predicts a uniform tensile strain on the top Si layer for any size of Si∕SiGe∕Si islands.

Experimental characterization and mechanical behavior analysis on intermetallic compounds of 96.5Sn-3.5Ag and 63Sn-37Pb solder bump with Ti-Cu-Ni UBM on copper chip

This study investigated the mechanical behavior of flip-chip lead-free solder bumps affected by solder/UBM intermetallic compound formation in the duration of isothermal aging. To attain the objective, test vehicles of Sn-Ag (lead-free) and Sn-Pb (lead-containing) solder bump systems were used to experimentally characterize and analyze their mechanical behavior. By way of metallurgical microscopy and SEM observation, the interfacial microstructure of test vehicles were measured and analyzed. In addition, a bump shear test is utilized for the strength determination of solder bumps. The results indicated that after isothermal aging treatment at 150/spl deg/C for over 1000 hours, the Sn-Ag solder revealed a better maintenance of bump strength than that of Sn-Pb solder, and the Sn-Pb solder showed a higher intermetallic compounds growth rate than that of Sn-Ag solder. In terms of the solder bump volume and the UBM size effects, both the Sn-Ag and the Sn-Pb solders showed no significant effect on the intermetallic compounds growth rate.

Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor

In this study, a packaged silicon base piezoresistive pressure sensor with thermal stress buffer is designed, fabricated, and measured. A finite element method (FEM) is adopted for design and experimental validation of the sensor performance. Thermal and pressure loading on the sensor is applied to make a comparison between sensor experimental and simulation results. Furthermore, a method that transfers simulation stress data into output voltage is proposed in this study, the results indicate that the experimental result coincides with simulation data.Copyright

Analysis and Validation of Thermal and Packaging Effects of a Piezoresistive Pressure Sensor

Abstract In this study, a packaged silicon base piezoresistive pressure sensor with thermal stress buffer is designed, fabricated, and studied. A finite element method (FEM) is adopted for designing and optimizing the sensor performance. Thermal and pressure loading on the sensor is applied to make a comparison between experimental and simulation results. Furthermore, a method that transforms simulation stress data into output voltage is proposed in this study, and the results indicate that the experimental result coincides with the simulation data. In order to achieve better sensor performance, a parametric analysis is performed to evaluate the system sensitivity, as well as thermal and packaging effects of the pressure sensor. The design parameters of the pressure sensor include membrane size, sensor chip size, glass thickness, adhesive layer thickness, PCB thickness/material, etc. The findings show that proper selection of the sensor structure and material not only enhances the sensor sensitivity but also reduces the thermal effects as well as the packaging influence.

Analysis and Validation of Sensing Sensitivity of a Piezoresistive Pressure Sensor

In this study, a packaged silicon based piezoresistive pressure sensor is designed, fabricated, and studied. A finite element method (FEM) is adopted for designing and optimizing the sensor performance. Thermal as well as pressure loading on the sensor is applied to make a comparison between experimental and simulation results. Furthermore, a method that transfers the simulation stress data into output voltage is proposed in this study, and the results indicate that the experimental result coincides with the simulation data. In order to achieve better sensor performance, a parametric analysis is performed to evaluate the system output sensitivity of the pressure sensor. The design parameters of the pressure sensor include membrane size/shape and the location of piezoresistor. The findings depict that proper selection of the membrane geometry and piezoresistor location can enhance the sensor sensitivity.Copyright