Chika Tanaka

High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions

High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky barrier transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi/sub 2/ process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

Threshold Voltage Control by Substrate Bias in 10-nm-Diameter Tri-Gate Nanowire MOSFET on Ultrathin BOX

We investigated the substrate bias effect in 10-nm-diameter tri-gate nanowire (NW) MOSFETs on ultrathin BOX. By employing a thin BOX of 20 nm and a thin NW body, a large body effect factor was achieved, which is sufficient for wide range <i>V</i>_th control. <i>I</i>_on-<i>I</i>_off adjustment by <i>V</i>_sub of 1 V or -1 V enabled a 13% increase in <i>I</i>_on or a one-order decrease in <i>I</i>_off, respectively. Negative <i>V</i>_sub could enlarge SRAM noise margin. Thus, a tri-gate NW MOSFET on ultrathin BOX is potential advantage for low power operation by adopting dynamic power and performance management.

10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V th tunability through thin BOX

We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with Vth tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and Ion of 1mA/μm at Ioff of 100nA/μm is achieved. We also demonstrate Vth control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40-50 nm, and its power is not small due to frequent refresh (retention time ~ 100μs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.

Experimental Study of Self-Heating Effects in Trigate Nanowire MOSFETs Considering Device Geometry

Temperature rise by self-heating effects in nanowire (NW) transistors (NW Trs.) is systematically studied with respect to their dependence on the structural parameters. Temperature rise in NW Tr. is found to be independent of the NW size in sub-100-nm regions when compared at the same total power consumption. This is because the heat generated by the drain current is spread to the area larger than the NW channel. Dependences of temperature rise on other parameters such as gate oxide or buried oxide thickness suggest that heat dissipates mainly via source/drain or substrate not via the gate electrode.

Systematic understanding of self-heating effects in tri-gate nanowire MOSFETs considering device geometry and carrier transport

Self-heating effects (SHE) in nanowire transistors (NW Tr.) have been systematically studied with respect to the dependence on the NW width (W), NW height (H), and gate length (L_g). Temperature rise (ΔT) by SHE in NW Tr. is smaller than SOI planar Tr. when compared with power consumption per unit area. Instead, ΔT at the same total power consumption (not normalized by area) is independent of W, H and L_g in sub-100nm regions, since the heated area does not scale with L_g and W. Drain current (I_d) reduction by SHE is almost constant for a wide range of L_g due to the weak temperature dependence of I_d in velocity saturation regime. I_d reduction in narrow NW Tr. is slightly less than that in wide NW Tr. because of the stronger velocity saturation at the same power consumption.

Performance, variability and reliability of silicon tri-gate nanowire MOSFETs

We systematically study short-channel performance, threshold voltage variability, and negative bias temperature instability in silicon tri-gate nanowire transistors (NW Tr.). By introducing epi S/D with thin gate spacer, on-current of NW Tr. is significantly improved for the same off-current thanks to the parasitic resistance (RSD) reduction. <;100>;-oriented NW channel further improves on-current as compared to <;110>; NW channel. In Pelgrom plot of σVth of NW Tr., there exists a universal line whose Avt is smaller than planar Tr. due to gate grain alignment. Deviation of the narrowest Tr. from σVth universal line is eliminated by suppressing RSD. Enhanced degradation by negative bias temperature stress in narrow NW Tr. can be attributed to the electric field concentration at the NW corner.

Experimental Study of Random Telegraph Noise in Trigate Nanowire MOSFETs

Random telegraph noise (RTN) in trigate nanowire transistors (NW Tr.) is systematically studied with respect to the NW size dependence. Time to capture and emission, which is related to the characteristic of the traps, such as trap energy, is independent of NW size. On the other hand, noise amplitude increases as the NW size decreases showing the similar size dependence to the reported scaled planar Tr. In addition, RTN after hot-carrier injection (HCI) and negative bias stress (NBS) is studied. HCI and NBS induce additional carrier traps, which generate larger noise signals. Since the degradation by HCI or NBS is larger with narrower width, RTN after these stresses is found to be severer in the NW Tr.

Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis

We proposed a compact model for tunneling field effect transistors (TFETs), which combines BSIM4. Our proposed model for tunneling current is based on a drift-diffusion model under the gradual-channel approximation. The total charge for the drain current has been described by a weighted sum of the tunneling charge and the oxide charge for gate-to-source overlap region. In order to obtain TFETs compact model for circuit simulation that operates in every voltage region, the operating current under the various gate-to-source voltage and drain-to-source voltage conditions are considered. Verilog-A description for our proposed model are implemented in the circuit simulator. Model parameters are extracted for conventional TFETs structure by comparing with in-house 2-D TCAD simulation results. After the transistor-level verification, the circuit-level simulation of 81-stage ring-oscillator using our proposed model has been performed.

Systematic study of RTN in nanowire transistor and enhanced RTN by hot carrier injection and negative bias temperature instability

We experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture (τ_c) and emission (τ_e) are independent of NW size, while threshold voltage fluctuation (ΔV_th) by RTN can be well fitted with 1/{L(W+2H)}^0.5 corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, ΔV_th is enhanced by HCI and NBTI and enhancement of ΔV_th becomes larger in narrower W.