Keiko Abe

Progress of STT-MRAM technology and the effect on normally-off computing systems

In this paper, the progress of P-MTJs is reviewed and prospects for the normally-off memory hierarchy based on new results are discussed.

Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU

We demonstrated lower power consumption of mobile CPU by replacing high-performance (HP)-SRAMs with spin transfer torque (STT)-MRAMs using perpendicular (p)-MTJ. The key points that enable the low power consumption are adapting run time power gating architecture (shown in Fig. 1), and satisfying both fast and low-power writing, namely, 3 nsec and 0.09 pJ, of p-MTJ cell (shown in Fig. 3). As shown in Table 1, only our developed p-MTJ has achieved 3 nsec, 0.09 pJ. Thanks to the fast and low-power p-MTJ, the power consumption of cache memory could be reduced by over 80% without degradation of performance.

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Nonvolatile memory, spin-transfer torque magnetoresistive RAM (STT-MRAM) is being developed to realize nonvolatile working memory because it provides high-speed accesses, high endurance, and CMOS-logic compatibility. Furthermore, programming current has been reduced drastically by developing the advanced perpendicular STT-MRAM [1]. Several-megabit STT-MRAM with sub-5ns operation is demonstrated in [2]. Advanced perpendicular STT-MRAM achieve ~3× power saving by reducing leakage current in memory cells compared with SRAM for last level cache (LLC) [3]. Such high-speed RAM applications, however, entail several issues: the probability of read disturbance error increases and the active power of STT-MRAM must be decreased for higher access speed. Moreover, the leakage power of peripheral circuits must be decreased, because the high-speed RAM requires high-performance transistors having high leakage current in peripheral circuitry [4], limiting the energy efficiency of STT-MRAM. To resolve these issues, this paper presents STT-MRAM circuit designs: a short read-pulse generator with small overhead using hierarchical bitline for eliminating read disturbance, a charge-optimization scheme to avoid excessive active charging/discharging power, and ultra-fast power gating and power-on adaptive to RAM status for reducing leakage power.

Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU

This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA).

Future prospects of MRAM technologies

This paper presents a review and future prospects for the tunnel magnetoresistance (TMR) effect in magnetic tunnel junction (MTJ) and spin manipulation technologies such as spin-transfer torque (STT) for magnetoresistive random access memory (MRAM). Major challenges for ultrahigh-density STT-MRAM with perpendicular magnetization and novel functional devices related to MRAM are discussed.

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture

We have proposed 3 nanoarchitectures with carbon nanotube-based nano-electromechanical systems (CNT-NEMS) switch with a floating gate. It is shown that logic based on them has the potential to replace CMOS using process technology of less than 45 nm. Furthermore, CNT-NEMS-based 3-D circuits realize extremely high bandwidth of over 10 petabyte/s with very low latency of less than several 10 ps. The most effective applications are 3D on-chip crossbar bus and future on-chip network, which will largely determine the performance of future microchips. The performance of 3-D on-chip crossbar based on CNT-NEMS is also compared with that based on CNT-transistors.

Ultra low power processor using perpendicular-STT-MRAM/SRAM based hybrid cache toward next generation normally-off computers

This paper presents novel processor architecture for HP-processor with MRAM/SRAM-based hybrid cache memory. By simulations of HP-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM [H. Yoda, et al., Current Appl. Phys. 10, e87 (2010)] can be reduced by 50.2% without any degradation of operation speed. This is the first report on effectively decreasing total power of HP-processors with no degradation of performance using magnetic memory. The presented architecture will be the first step to realize the next generation “normally-off computers.”

Low power and high density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques

Since it has been difficult to increase clock frequency of processors due to power budget, there is a trend toward increase in number of processor cores and cache capacities (Fig. 1) to improve the processor performance. According to this trend, there have been two serious issues on the cache memories. One issue is large leakage power of SRAM-based cache (Ex. About 80% of average processor power in a mobile usage case [1]). Another one is large memory area of SRAM especially for last level cache (LLC) like L4 cache. Recently, eDRAM is used to reduce memory area for LLC (Fig. 1). However, gate length of eDRAM is difficult to be reduced less than 40-50 nm, and its power is not small due to frequent refresh (retention time ~ 100μs.). To reduce the cache power and decrease memory area further at the same time, advanced STT-MRAM based cache has been considered promising from theoretical analysis [2]. However, both low power and high density LLC have not been ever clarified based on a realistic MTJ (magnetic tunneling junction) integration and circuit design. This paper presents solutions for the power and memory density with more advanced STT-MRAM cell technologies by low-temperature process development and novel cache memory architecture based circuit design.

Variable nonvolatile memory arrays for adaptive computing systems

Magnetic RAM (MRAM) has a unique potential to change its memory capacity from small to large capacity. This paper presents a novel variable circuit based on 1T-1MTJ of perpendicular STT-MRAM memory arrays. It can cover all memory hierarchy and computing units that are variable and adjustable to applications by selecting single, dual or quadruple cell mode and changing circuit resources.

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory

This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce static power consumptions compared to the conventional SRAM, because there are no static leakage paths in the D-MRAM cell and it is not needed to supply voltage to its cells when used as the MRAM-mode. Besides, with advanced perpendicular magnetic tunnel junctions (p-MTJ), which decreases the write energy and latency without shortening its retention time, D-MRAM is capable of power reduction by replacing the traditional SRAM caches. Considering the 65-nm CMOS technology, the access latencies of 1MB memory macro are 2.2 ns / 1.5 ns for read / write in DRAM mode, and 2.2 ns / 4.5 ns in MRAM mode, while those of SRAM are 1.17 ns. The SPEC CPU2006 benchmarks have revealed that the energy per instruction (EPI) of the total cache memory can be dramatically reduced by 71 % on average, and the instruction per cycle (IPC) performance of the D-MRAM cache architecture degraded only by approximately 4 % on average in spite of its latency overhead.