Toshinori Numata

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement of electron and hole mobilities of strained-SOI devices against the universal mobility amounts to 85 and 53%, respectively. On the other hand, we have also observed the reduction of carrier mobility in a thinner strained-Si layer or at higher vertical electric field conditions. For the first time, we have demonstrated a high-speed CMOS ring-oscillator using strained-SOI devices, and its improvement amounts to 63% at the supply voltage of 1.5 V, compared to control-SOI CMOS.

High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate

We demonstrate high performance CMOS operation of fully depleted (FD) and partially depleted (PD) strained-SOI MOSFETs on a new thin-film-SGOI substrate with high Ge content (25%) fabricated by the combination of SIMOX and ITOX technologies, without using the usual thick SiGe buffer layers. We verify high electron (85%) and hole (50%) mobility enhancement of strained-SOI MOSFETs against the universal carrier mobility. It is demonstrated, as a result, that the gate delay time of strained-SOI CMOS is improved by about 70%, compared to that of control-SOI CMOS. Moreover, we also discuss both the strained-Si thickness and the effective field dependent difference between electron and hole mobility enhancement factors of strained-SOI CMOS.

Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs

The characteristics of ultrathin-body (UTB) SOI MOSFETs, whose SOI-channel thickness T/sub SOI/ is thinner than the inversion-layer thickness of bulk MOSFETs, are investigated. It is found for the first time that at low temperatures (<50 K) the mobility of the UTB MOSFETs coincides with that of thicker body SOI MOSFETs in spite of the fact that at room temperature the mobility of UTB MOSFETs decreases as T/sub SOI/ decreases. It is experimentally demonstrated for the first time that the gate-channel capacitance of the UTB MOSFETs increases as T/sub SOI/ decreases. In addition, it is demonstrated that the physical origins of the threshold voltage increase in UTB MOSFETs can be categorized as mobility degradation and a subband energy level increase. All these results are consistently explained in terms of quanturn-mechanical effects.

Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices

This paper presents a quantitative study on the device design for the control of threshold-voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device simulation is used for this purpose, with emphasis on the impact of band offset in Si/SiGe heterostructures. For the control of threshold-voltage, the combination of the gate work function and the back gate bias is needed to obtain appropriate values of threshold-voltage in n- and p-channel MOSFETs and to suppress SiGe buried channels in p-channel MOSFETs with thicker strained-Si layers. Regarding SCEs, the importance and the necessity of thin SiGe layers are pointed out from the viewpoint of the influence of the higher permittivity of SiGe layers. It is shown that the SCEs of strained-SOI MOSFETs with thinner SiGe layers are almost the same level as those of unstrained-SOI.

Device Design and Electron Transport Properties of Uniaxially Strained-SOI Tri-Gate nMOSFETs

We propose effective subband engineering for electron mobility enhancement on a (110) surface, utilizing uniaxial tensile strain along (110) direction. This strain causes the re-population of electrons from fourfold valleys to twofold valleys, resulting in high mobility enhancement along the (110) direction. Using this concept, a 2.0x mobility enhancement in uniaxially strained silicon-on-insulator (SOI) trigate nMOSFETs with (110) sidewall channels has been realized. Here, the uniaxial tensile strain is applied by using anisotropic strain relaxation of biaxiallv strained-SOI substrates. It is also found that (110) current (strain) direction is the best for strained trigate nMOSFETs, suggesting that optimum multigate CMOS structures with enhanced mobility of both electrons and holes can be realized on a conventional (001) wafer in the same (110) current flow direction for nMOSFETs and pMOSFETs.

High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on globally (biaxially) strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET. This high mobility enhancement is maintained in high vertical effective fields as well as in short-channel devices. As a result, significant ION enhancement of 80% is demonstrated in 40-nm gate-length uniaxially strained SGOI pMOSFET

Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs

Uniaxial and biaxial strain additive mobility enhancements and their physical understandings are experimentally examined by applying mechanical stress to high mobility channel materials. As for nMOSFETs, <110> uniaxial and biaxial tensile strain are partially additive in the electron mobility enhancement due to the conduction band warping and resulting effective mass reduction under shear strain. As for pMOSFETs, it is found that an initial compressive biaxial strain is efficient to boost the impact of the shear strain component in the <110> uniaxial strain on hole mobility, demonstrating the effectiveness in combining uniaxial and biaxial stress for strained SiGe channels. The piezoresistance coefficients for (001) Germanium pMOSFETs are also experimentally evaluated for the first time.