Masumi Saitoh

Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs

The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It is shown that the mobility in [110] UTB pMOSFETs, which is much higher than the universal curve in conventional (100) pMOSFETs, is not degraded until t/sub SOI/ is thinned to 3 nm. Scattering mechanisms in [110] UTB pMOSFETs are discussed on the basis of the temperature dependence of the mobility. The high mobility in the UTB regime in [110] pMOSFET is attributed to subband modulation by carrier confinement and heavier hole effective mass normal to the channel surface.

Extension of Coulomb blockade region by quantum confinement in the ultrasmall silicon dot in a single-hole transistor at room temperature

First room-temperature (RT) observation of extended Coulomb blockade (CB) region due to quantum confinement in the ultrasmall silicon dot in a single-hole transistor (SHT) is described. We fabricate single-dot SHTs in the form of metal-oxide-semiconductor field-effect transistors with an extremely constricted channel. Both large CB oscillation with the peak-to-valley current ratio (PVCR) of 40.4 and clear negative differential conductance (NDC) with the PVCR of 11.8 (highest ever reported) are observed at RT in the fabricated device. The observed NDC is attributable to the resonant tunneling due to the large quantum level spacing in the ultrasmall dot whose size is estimated to be about 2 nm.

Large memory window and long charge-retention time in ultranarrow-channel silicon floating-dot memory

We propose and demonstrate an ultranarrow-channel silicon floating-dot memory, in which the channel width is scaled to sub-10 nm. In the fabricated ultranarrow-channel memory, a larger threshold voltage shift has been observed than in the wide-channel memory. From numerical calculations, it turns out that this is caused by bottleneck regions that dominate the conductance of the whole channel in the ultranarrow-channel. Moreover, longer charge-retention time has been also obtained in the fabricated ultranarrow-channel memory. This can be explained by the nonlinear dependence of the threshold voltage shift on the number of electrons in the dots due to the classical bottleneck effect and the increase in the ground state energy of the channel due to the quantum confinement.

Large Electron Addition Energy above 250 meV in a Silicon Quantum Dot in a Single-Electron Transistor

We demonstrate large Coulomb blockade oscillations in a silicon single-electron transistor (Si SET) whose peak-to-valley ratio is about 2 at room temperature. The device is fabricated in the form of a point-contact metal-oxide-semiconductor field-effect transistor (MOSFET) and the gate oxide is formed by chemical vapor deposition (CVD) instead of thermal oxidation. From the analysis of current-voltage characteristics, it is found that the single-electron addition energy is about 259 meV and the dot diameter is less than 4.4 nm. The mechanism of silicon dot formation is also discussed.

Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs

Threshold voltage variation due to quantum confinement effect in ultra-thin body silicon-on-insulator (SOI) MOSFETs is examined. It is experimentally demonstrated that threshold voltage variation drastically increases when SOI layer is thinned down to 3 nm. A percolation model is used to estimate the contribution of surface roughness to V/sub th/ variation. The method to suppress the threshold voltage variation is also proposed, and around 15% reduction in threshold voltage variation is experimentally demonstrated by applying substrate bias. The reason of the suppression can be explained by quantum confinement effect induced by substrate bias.

Carrier Transport in (110) nMOSFETs: Subband Structures, Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress Engineering

(110) surface orientation have attracted great interests, since pFETs on (110) substrates show much superior mobility to (100) pFETs (Sun, et. al., 2005 and Sato, et, al, 1969). In addition, (110) surface orientation is widely utilized in advanced FET structures such as FinFETs (Liow, 2005) and Tri-gate FETs (Kavalieros, 2005). Thus, there are growing interests in whether, how, and how far the electron mobility, mue, of (110) nFETs can be improved. A few reports have been made on carrier transports in (110) nFETs (Irie, et. al., 2004) its physical mechanisms and stress dependence have not been fully investigated nor understood yet. In this paper, mue of (110) nFETs is studied in terms of channel direction, Ns, and temperature dependences to clarify the carrier transport mechanisms in (110) nFETs. In addition, the impact of stress engineering is investigated in terms of mue enhancements to provide the guidance to boost (110) nFETs performance

Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor

We investigate electron transport through the ultrasmall silicon quantum dot in a single-electron transistor. The device is fabricated in the form of a silicon point-contact channel metal–oxide–semiconductor field-effect transistor. The size of the formed dot is estimated to be as small as 5.3 nm. Negative differential conductance is clearly observed up to 25 K. It turns out that this is caused by discreteness of quantum levels in the silicon dot and variation of the tunneling rates to each level. The fine structure of conductance persists up to 77 K. Modeling of the electron transport through the silicon dot is carried out. Good agreement between experiment and calculation is obtained, which confirms the validity of our model.

Room-temperature demonstration of integrated silicon single-electron transistor circuits for current switching and analog pattern matching

This paper reports the first room-temperature (RT) operation of integrated single-electron transistor (SET) circuits. We fabricate silicon single-hole transistors (SHTs) with high controllability and obtain large Coulomb blockade (CB) oscillation with the peak-to-valley current ratio (PVCR) of over 10/sup 3/ at RT. A current switch using two SHTs integrated under a single gate is demonstrated at RT. We propose a novel application of SHTs, an ultra-compact analog pattern matching circuit. Its basic operation is demonstrated at RT using three SHTs fabricated on one chip, whose CB peak positions and currents are properly controlled by hole injection into nanocrystals embedded in the gate oxide of SHTs.

Voltage gain dependence of the negative differential conductance width in silicon single-hole transistors

The full width at half maximum (FWHM) of the negative differential conductance (NDC) characteristics in room temperature (RT)-operating silicon single-hole transistors (SHTs) has been studied by experiments and calculations. It is found that when the voltage gain of the SHT is higher, sharper NDC and smaller FWHM are achieved. Lower drain coupling is considered to be the main reason for the small FWHM in a resonant tunneling system of RT-operating SHTs. FWHM of NDC of as small as 95mV has been obtained in a SHT with the gain of as high as 5.2 at RT, which is the highest value of the gain ever reported. The device is in the form of an ultranarrow wire channel metal oxide semiconductor field-effect transistor, which shows large Coulomb blockade oscillations at RT and has extremely small drain capacitance due to its ultranarrow channel structure. NDC can now be designed by device parameters, showing further potential for application to low-voltage, low-power NDC circuits.

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.