Chimoon Huang

Mechanisms of interface trap-induced drain leakage current in off-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFETs after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO/sub 2/ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 /spl mu/m n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V/sub dg/). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression /spl Delta/I/sub d/=Aexp(B/sub it//F). The value of B/sub it/ about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V/sub dg/ decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V/sub dg/, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant. >

Color-tunable multilayer light-emitting diodes based on conjugated polymers

Wide-range low-voltage continuous color tuning is achieved in multilayer light-emitting diodes based exclusively on the commonly used high-efficiency electroluminescent conjugated polymers. There are three layers for red, green, and blue emission, and one extra layer for electron blocking. The color of the emitted photon depends on the position of the electron-hole recombination. Due to the stronger field dependence of the electron mobility relative to the hole mobility, the recombination zone is pushed away from the cathode and concentrated in different emissive layers as the voltage increases.

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10/sup 4/ times more efficient in trap generation than the hot electron stress in terms of injected charge.

Hot hole stress induced leakage current (SILC) transient in tunnel oxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-/spl Aring/ oxide obeys a power law time dependence f/sup -n/ with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed.

Modeling hot-electron gate current in Si MOSFET's using a coupled drift-diffusion and Monte Carlo method

A coupled two-dimensional drift-diffusion and Monte Carlo analysis is developed to study the hot-electron-caused gate leakage current in Si n-MOSFETs. The electron energy distribution in a device is evaluated directly from a Monte Carlo model at low and intermediate electron energies. In the region of high electron energy, where the distribution function cannot be resolved by the Monte Carlo method due to limited computational resources, an extrapolation technique is adopted with an assumption of a Boltzmann tail distribution. An averaging method is employed to extract the effective electron temperature. Channel hot electron injection into a gate via quantum tunneling and thermionic emission is simulated, and electron scattering in the gate oxide is taken into account. The calculated values of gate current are in good agreement with experimental results. The simulation shows that the most serious hot electron injection occurs about 200-300 AA behind the peak of average electron energy due to a delayed heating effect. >

Effects of hot carrier induced interface state generation in submicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 /spl mu/m LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V/sub g//spl sime/0.5 V/sub d/ in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states. >

Interface trap induced thermionic and field emission current in off-state MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state MOSFETs after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si-SiO/sub 2/ interface by hole emission from interface traps to the valence band and electron emission from interface traps to the conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In experiment, a 0.5 /spl mu/m n-MOSFET was subject to hot carrier stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, is responsible for the leakage current at a large drain-to-gate bias (V/sub dg/) The lateral field plays a dominant role in the two-step tunneling process. As V/sub dg/ decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V/sub dg/, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron hole pairs through traps is dominant.<<ETX>>

Temperature dependence of time-resolved photoluminescence spectroscopy in InAs/GaAs quantum ring

We present detailed experimental results of the temperature dependence of continuous wave and time-resolved photoluminescence (PL) spectroscopy in self-assembled InAs/GaAs quantum dot and quantum ring nanostructures. A dramatic increase in PL decay time of the excited and ground states is observed in InAs quantum rings at high temperature. We speculate that the longer PL lifetime in quantum rings is due to the interplay among the dark states, ground states, and the reduced wave function overlapping between electrons and holes. A rate equation model is proposed to interpret the observed temperature dependence of the ground state exciton lifetime.

Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant.

Interface trap effect on gate induced drain leakage current in submicron N-MOSFET's

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5//spl mu/m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress. The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of /spl Delta/I/sub d/=A exp(-B/sub u//F) with a value of B/sub u/ of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling. >