Weiru Gu

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. This opamp split-sharing scheme mitigates the memory effect without a dedicated clock phase and avoids crosstalk. In the back-end ADC, 4.5-bit opamp-sharing MDACs with four-input operational trans-conductance amplifiers (OTAs) are used for further power saving. Implemented in a 0.18-μm CMOS process, the 14-bit ADC achieves a spurious-free dynamic range (SFDR) of 89.1 dB and a signal-to-noise plus distortion ratio (SNDR) of 70.2 dB, with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB, respectively. The ADC consumes 92 mW with a 1.8-V supply, occupying an area of 6.3 mm2.

Power efficient SAR ADC with optimized settling technique

This paper presents a 12-bit 50-MS/s successive-approximation (SAR) analog-to digital (ADC) with high power efficiency. By splitting MSB capacitors an efficient step switching scheme is proposed to reduce average switching energy of the capacitive DAC by 93.75% as compared to conventional method. The settling time is partially optimized in half of the conversion steps. Prototype is designed in a 65-nm CMOS technology and the power consumption is 2.0mW under a 1.2-V power supply.

A wide-range and high-precision real-time calibration for dynamic comparator

In this paper, a high-precision and high-linearity calibration is introduced for dynamic comparator offset using I-MOS capacitors. After calibration, the offset can be reduced from 29.9 mV to 66 μV (one sigma) at 2GHz working clock. Simulation results show that the SFDR and the SNDR can be improved 20dB in a case of 12bit 50MS/s successive approximation analog to digital converter (SAR ADC) with the proposed calibration method at the expense of 30 μW power consumption.

A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique*

This paper presents a single-ended 8-channel 10-bit 200 kS/s 607 μW synchronous successive approximation register (SAR) analog-to-digital converter (ADC) using HLMC 55 nm low leakage (LL) CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607 μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and-distortion ratio (SNDR) is 60.1 dB and the spurious-free dynamic range (SFDR) is 68.1 dB. The measured DNL is +0.37/−0.06 LSB and INL is +0.58/−0.22 LSB.