Mingshuo Wang

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

This paper presents a power-efficient, high-linearity pipelined ADC, utilizing a combined front-end of the sample/hold circuit (S/H) and the first multiplying digital-to-analog converter (MDAC1). In contrast with the conventional merged sample-and-hold amplifier (SHA) and first MDAC, the front-end uses an opamp split-sharing scheme to meet the different gain and bandwidth requirements of both the S/H and the first MDAC. This opamp split-sharing scheme mitigates the memory effect without a dedicated clock phase and avoids crosstalk. In the back-end ADC, 4.5-bit opamp-sharing MDACs with four-input operational trans-conductance amplifiers (OTAs) are used for further power saving. Implemented in a 0.18-μm CMOS process, the 14-bit ADC achieves a spurious-free dynamic range (SFDR) of 89.1 dB and a signal-to-noise plus distortion ratio (SNDR) of 70.2 dB, with a sampling rate of 100 MS/s and an input of 15.5 MHz. For input signals up to 220 MHz, measured SFDR and SNDR are maintained above 82.7 dB and 66.2 dB, respectively. The ADC consumes 92 mW with a 1.8-V supply, occupying an area of 6.3 mm2.

A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC

A single-channel 1.0-GS/s 8-bit Voltage-Buffer-Free Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the chip area grandly. An improved single-diode switch with an extra reset path is proposed as inter-stage sampling switches. The ADC implemented in 65nm CMOS technology achieves SNDR of 47.5 dB and SFDR of 57.8 dB for 487.3 MHz input frequency at the rate of 1.0-GS/s. The power consumption is 75 mW with supply voltage of 1.2 V.

A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier

This paper presents a new low offset comparator with a mismatch-suppressed dynamic preamplifier Various mismatches contribute to comparatorss input referred offset. The proposed mismatch suppression is achieved by sampling the mismatches at the dynamic preamplifiers output node during the precharge phase. A time-domain analysis method is utilized to quantize the suppression effects. By the techniques, a 1-GS/s four-input comparator is implemented by 65-nm CMOS technology. It achieves a 60-μW power dissipation and a 1.89-mV 1-sigma(σ) offset voltage, which is a 90% improvement compared to its non-suppressed counterparts.

A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding

This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAIADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-μm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498MHz input frequency at the rate of 1.0GS/s. The power consumption is 98mW with sampling rate of 1.0GS/s and supply voltage of 1.2/ 2.5V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step.

A cancellation technique for output-dependent delay differences in high-accuracy DACs

For high-accuracy digital-to-analog converter (DAC), delay difference depending on output voltage is one of the major nonlinearities that deteriorate the dynamic performance. In this paper, an improved output-dependent delay cancellation (ODDC) technique is proposed. The proposed ODDC is implemented in simple circuit architecture and has advantages of significant improvement on the dynamic performance in a wide frequency range without increasing the noise floor. ODDC can eliminate the switching instant variations caused by output voltage of DAC through tuning the bulk voltage of switches in the deep N-well. The algorithm of ODDC technique is derived. A 1GS/s 14 bits current-steering DAC with proposed ODDC is simulated and the SFDR can be improved significantly with proper circuit parameters.

A wide-range and high-precision real-time calibration for dynamic comparator

In this paper, a high-precision and high-linearity calibration is introduced for dynamic comparator offset using I-MOS capacitors. After calibration, the offset can be reduced from 29.9 mV to 66 μV (one sigma) at 2GHz working clock. Simulation results show that the SFDR and the SNDR can be improved 20dB in a case of 12bit 50MS/s successive approximation analog to digital converter (SAR ADC) with the proposed calibration method at the expense of 30 μW power consumption.

A 1.0 GS/s 7bit Pipelined-Folding-Interpolating ADC with 6.0 ENOB at nyquist frequency

A single-channel 1.0 GS/s 7bit Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. A fine and coarse joint encoding method is proposed to simplify the analog preprocessing of the coarse sub-ADC and to save power and chip area. Double-diode bootstrapped interstage switch is adopted to improve the overall efficiency of speed. The ADC implemented in 0.13-μm CMOS achieves SNDR of 37.89 dB and SFDR of 45.89 dB for 498MHz input frequency located at 1.0GS/s. The power consumption is 110mW with sampling rate of 1.0GS/s and supply voltage of 1.5/2.5 V.

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network

In this paper, a 1.5-GS/s 5-bit interpolating analog-to-digital converter (ADC) with offset averaging and interpolating sharing resistors network (OAISRN) is presented. The proposed OAISRN is based on conventional flash ADC and the concept of zero crossing points in folding and interpolating architecture. In order to reduce power dissipation yet to make a high performance, it removes half of preamplifiers and ensures matching by using offset averaging and 2x-interpolation sharing resistors network behind the initial zero crossing points generators array. Implementation of the OAISRN is explained in detail and its impact on signal bandwidth is discussed. The interpolating ADC in TSMC 65 nm process achieves SNDR of 27.8 dB and SFDR of 37.7 dB for 745 MHz input frequency located at 1.5 GS/s in postsimulation. The power consumption is 9.6 mW under a supply voltage of 1.2 V.

A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth

A 1.0 GHz signal bandwidth 8-bit folding and interpolating analog-to-digital converter (ADC) is presented, whose Fom is only 42 fJ/Conv-step. In this design, averaging resistors and interpolating resistors are shared, which can be save pr-amplifiers and active interpolators. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new fulldigital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the area of chip grandly. A new linear and continues offset voltages of dynamic comparator calibration method is presented. This ADC implemented in 65 nm CMOS technology achieves SNDR of 48.5 dB and SFDR of 58.7 dB for 479.5 MHz input frequency at the rate of 1.0-GS/s. And the SNDR and SFDR maintain above 48 dB and 55 dB, respectively, up to 995.1 MHz. The power consumption is only 17 mW with a supply voltage of 1.2 V.