Chris M. Breslin

Sub-10 nm carbon nanotube transistor.

This first demonstration of CNT transistors with channel lengths down to 9 nm shows substantially better scaling behavior than theoretically expected. Numerical simulations suggest that a possible explanation for the surprisingly good performance is a result of the gate modulating both the charge in the channel and in the contact regions. The unprecedented performance should ignite exciting new research into improving the purity and placement of nanotubes, as well as optimizing CNT transistor structure and integration. Results from aggressively scaling these molecular-channel transistors exhibit their strong suitability for a low-voltage, high-performance logic technology.

Carbon Nanotube Complementary Wrap-Gate Transistors

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Vertical III-V nanowire device integration on Si(100).

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: towards monolithic integration of nano-devices

We demonstrate a catalyst-free growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. The nanotube template is selectively filled by homo- as well as heteroepitaxial growth of nanowires with the morphology entirely defined by the template geometry. To demonstrate the method single-crystalline InAs wires on Si as well as InAs-InSb axial heterostructure nanowires are grown within the template. The achieved heterointerface is very sharp and confined within 5-6 atomic planes which constitutes a primary advantage of this technique. Compared to metal-catalyzed or self-catalyzed nanowire growth processes, the nanotube template approach does not suffer from the often observed intermixing of (hetero-) interfaces and non-intentional core-shell formation. The sequential deposition of different material layers within a nanotube template can therefore serve as a general monolithic integration path for III-V based electronic and optoelectronic devices on silicon.

Demonstration of a High Extinction Ratio Monolithic CMOS Integrated Nanophotonic Transmitter and 16 Gb/s Optical Link

We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach-Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal-semiconductor-metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

Sub-10 nm carbon nanotube transistor

This first demonstration of CNT transistors with channel lengths down to 9 nm shows substantially better scaling behavior than theoretically expected. Numerical simulations suggest that a possible explanation for the surprisingly good performance is a result of the gate modulating both the charge in the channel and in the contact regions. The unprecedented performance should ignite exciting new research into improving the purity and placement of nanotubes, as well as optimizing CNT transistor structure and integration. Results from aggressively scaling these molecular-channel transistors exhibit their strong suitability for a low-voltage, high-performance logic technology.

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a room-temperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET Ion performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kanes tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.

Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme

In this work, we report electrical characterization FinFET devices with 29nm-pitch fins patterned using a technique called tone inverted grapho-epitaxy (TIGER). We use a topographic template to direct the self-assembly of block copolymers (BCP) to form small area gratings that are self-aligned to the template. After a tone-inversion operation, blocks of defect free SOI fins bounded by self-aligned exclude regions are formed with the spacing determined by the template line width (LW). This self-aligned customization enables further definition of the active region for FinFETs. Process window and design implications for directed self-assembly (DSA) with TIGER are also discussed.