Lynne M. Gignac

Sub-10 nm carbon nanotube transistor.

This first demonstration of CNT transistors with channel lengths down to 9 nm shows substantially better scaling behavior than theoretically expected. Numerical simulations suggest that a possible explanation for the surprisingly good performance is a result of the gate modulating both the charge in the channel and in the contact regions. The unprecedented performance should ignite exciting new research into improving the purity and placement of nanotubes, as well as optimizing CNT transistor structure and integration. Results from aggressively scaling these molecular-channel transistors exhibit their strong suitability for a low-voltage, high-performance logic technology.

Mechanisms for microstructure evolution in electroplated copper thin films near room temperature

We present a model which accounts for the dramatic evolution in the microstructure of electroplated copper thin films near room temperature. Microstructure evolution occurs during a transient period of hours following deposition, and includes an increase in grain size, changes in preferred crystallographic texture, and decreases in resistivity, hardness, and compressive stress. The model is based on grain boundary energy in the fine-grained as-deposited films providing the underlying energy density which drives abnormal grain growth. As the grain size increases from the as-deposited value of 0.05–0.1 μm up to several microns, the model predicts a decreasing grain boundary contribution to electron scattering which allows the resistivity to decrease by tens of a percent to near-bulk values, as is observed. Concurrently, as the volume of the dilute grain boundary regions decreases, the stress is shown to change in the tensile direction by tens of a mega pascal, consistent with the measured values. The small ...

Reduced electromigration of Cu wires by surface coating

Electromigration in on-chip Cu interconnections with a selective electroless metal coating, CoWP, CoSnP, or Pd, on the top surface of Cu damascene lines has been investigated. The 10–20 nm thick metal cap significantly improves electromigration lifetime by providing protection against interface diffusion of Cu which has been the leading contributor to metal line failure by electromigration.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Reduced Cu interface diffusion by CoWP surface coating

Electromigration in Cu interconnections with a 10-nm thick selective electroless CoWP coating on the top surface of Cu dual damascene lines has been investigated. The grain structures of the lines embedded in SiLK semiconductor dielectric ranged from bamboo-like to polycrystalline. CoWP coated structures exhibited a greatly improved Cu electromigration lifetime which was attributed to a reduction in Cu interface diffusion.

Interfacial reactions of Sn-Ag-Cu solders modified by minor Zn alloying addition

The near-ternary eutectic Sn-Ag-Cu alloys have been identified as leading Pb-free solder candidates to replace Pb-bearing solders in microelectronic applications. However, recent investigations on the processing behavior and solder joints reliability assessment have revealed several potential reliability risk factors associated with the alloy system. The formation of large Ag3Sn plates in Sn-Ag-Cu joints, especially when solidified in a relatively slow cooling rate, is one issue of concern. The implications of large Ag3Sn plates on solder joint performance and several methods to control them have been discussed in previous studies. The minor Zn addition was found to be effective in reducing the amount of undercooling required for tin solidification and thereby to suppress the formation of large Ag3Sn plates. The Zn addition also caused the changes in the bulk microstructure as well as the interfacial reaction. In this paper, an in-depth characterization of the interfacial reaction of Zn-added Sn-Ag-Cu solders on Cu and Au/Ni(P) surface finishes is reported. The effects of a Zn addition on modification of the interfacial IMCs and their growth kinetics are also discussed.

Carbon Nanotube Complementary Wrap-Gate Transistors

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps

Electromigration in Cu Damascene lines with bamboo-like grain structures, either capped with Ta/TaN, SiNx, SiCxNyHz layers, or without any cap, was investigated. A thin Ta/TaN cap on top of the Cu line surface significantly improves electromigration lifetime when compared with lines without a cap and with lines capped with SiNx or SiCxNyHz. The activation energy for electromigration increased from 0.87 eV for lines without a cap to 1.0–1.1 eV for samples with SiNx or SiCxNyHz caps and to 1.4 eV for Ta/TaN capped samples.

High-quality aluminum oxide gate dielectrics by ultra-high-vacuum reactive atomic-beam deposition

We demonstrate the potential for ultrathin aluminum-oxide films as alternate gate dielectrics for Si complementary metal–oxide–semiconductor technology. Films are deposited in ultrahigh vacuum utilizing atomic beams of aluminum and oxygen on Si(100) surfaces. We show device-quality Si(100)/Al2O3 interfaces with interfacial trap densities in the 1010 cm−2 eV−1 range, and with leakage current densities five orders of magnitude lower than what is observed in SiO2 insulators at the same equivalent electrical thickness. As-grown films possess an amorphous-to-microcrystalline structure, depending upon the deposition temperature, and any interfacial layers between the Si(100) and Al2O3 layer are <∼0.5 nm.

Mechanisms for very long electromigration lifetime in dual-damascene Cu interconnections

Electromigration in 0.27 μm wide Cu damascene interconnections has been investigated. The results show that the electromigration time to failure of Cu interconnections is greatly influenced by the thickness of the metal liner at the contact between the via and underlying line. A remarkably long lifetime was achieved when a 3 nm thick liner (at the via/metal line interface) was used, since the abrupt mass flux divergence at this interface normally seen is greatly diminished. Voids were found in the regions where there was no electric field and on the bamboo Cu grain structure. Void formation is explained by the effect of a vacancy wind.