Dan Oh

Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems

Accurate modeling of transmission lines becomes increasingly important in high-speed interconnect system design. However, it is rather difficult to obtain broadband transmission line models, in particular using frequency-domain measurements. This paper points out two potential accuracy issues. First, inaccurate DC values of the frequency-domain data cause a severe error in the time-domain simulations. Second, it is difficult to characterize the characteristic impedance over a wide frequency range due to the reflection caused by the port discontinuities. This paper proposes the combination of both time and frequency measurement data to mitigate the DC accuracy issue. For the characteristic impedance model, a new de-embedding technique is presented to mitigate the port discontinuity issue. Several numerical examples, such as MCM-L coplanar lines and package microstrip lines, are studied to validate the accuracy of the proposed method.

Multiple Edge Responses for Fast and Accurate System Simulations

Fast and accurate simulation of the system response is important in high-speed I/O system design because performance is severely limited by channel ISI and random noise. This paper presents a novel way to simulate the signal response given an arbitrary bit pattern using multiple edge responses (MER). The presented method provides an accuracy improvement over the traditional approaches which either uses the superposition of single bit response (SBR) or double edge response (DER), while maintaining the equivalent numerical efficiency

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

This paper describes the design and characterization of a low power differential memory interface targeted for mobile applications. The initial design of the memory interface achieves 2.7 to 4.3GB/s data bandwidth and consumes 3.3mW/Gb/s at 4.3GB/s operation. The design allows two x16 stacked dies to be fit into a 12mm PoP package, achieving a 12.8GB/s aggregated data bandwidth based on 3.2Gb/s per pin. A low swing signaling based on a voltage-mode differential driver is reviewed and its performance is analyzed. We demonstrate that, compared to LPDDR2 memory interface based on single-ended signaling, the differential memory interface overcomes most of channel related issues such as crosstalk and SSO noise and provides a very clean channel response. Thus, the resulting extra system margin can be used to compensate for extra timing jitter and system noise, enabling lower power and lower system cost. To evaluate the impact of timing jitter and system noise to system performance, a statistical link modeling and simulation methodology is employed. Two test systems are built based on wirebond-based Package-on-Package (PoP) and BGA-based Chip-to-Chip (C2C) module to characterize the memory system performance and to validate the memory statistical link model. The correlation result showed a good agreement in the system bit error rates (BER) between measurement and simulation.

Jitter Amplification Considerations for PCB Clock Channel Design

Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

Precursor ISI Reduction in High-Speed I/O

To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves performance for most channels. This is due to the interaction between equalization adaptation and clock-data recovery (CDR), coupled with transmitter peak-power constraint. To minimize the impact of precursor ISI on the bit-error-rate (BER), we propose a new method of adapting CDR phase for maximum voltage margin.

Jitter modeling in statistical link simulation

Modern high-speed I/O link design requires accurate modeling and simulation of various jitter types including both deterministic and random jitter components. Transient simulators such as SPICE have successfully modeled deterministic jitter but they have limited capabilities to model random jitter. A statistical approach has been recently employed to handle jitter more efficiently. This paper presents a general jitter model suitable for a statistical simulation framework. The proposed model can accurately account for transmitter and receiver random jitter with any distribution and power spectrum density. We have also extended the proposed model to derive a closed-form formula for modeling transmitter clock jitter. The presented methodology is validated using both time-domain simulation and lab measurement.

Prediction of System Performance Based on Component Jitter and Noise Budgets

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIOreg parallel link interface. Then, we apply the proposed methodology to a PCI Expressreg bus system to estimate the system performance based on published component jitter specification.

In-situ characterization of 3D package systems with on-chip measurements

Characterization of I/O channels in 3D package systems is quite challenging as it is difficult to observe signal quality. A traditional way of measuring each device in a component level does not capture complex interaction in 3D integration. Although a sense line can be designed to externally measure noise on power lines, it is not feasible for signal lines as it significantly alters the signal quality. Hence, on-chip measurement features are highly desirable for 3D package systems including emerging Through-Silicon Vias (TSV) technology. In this paper, four key on-chip measurement concepts and circuitries are reviewed: eScope for measuring overall link margins, eWave for capturing a signal waveform, nScope for generating and monitoring on-chip power noise, and zScope for measuring power distribution network (PDN). These circuitries are implemented in a low power differential memory interface. The test vehicle is built based on Package-on-Package (PoP) environment. Measurements from the test vehicle are compared with the predicted data based on simulation.

Challenges and solutions for next generation main memory systems

Todays high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view.