Chuck Yuan

Clocking and circuit design for a parallel I/O on a first-generation CELL processor

A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of /spl plusmn/12mV at 6.4Gbit/s with BER <10/sup -14/ measured using 7b PRBS data.

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Modeling and analysis of power distribution networks for gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes increasingly important to accurately characterize and analyze power distribution networks (PDN). This paper presents the modeling, simulation, and measurement of a PDN in a high-speed FR4 printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps and above. The test board consists of two transceiver chips placed on wire bond plastic ball grid array (PBGA) packages. The applied analysis method is a hybrid technique that combines the interactions of the power planes, interconnects, and the nonlinear drivers. The power planes and interconnects are modeled using the transmission matrix method (TMM) and rational interpolation, respectively. Then macro modeling is applied to generate reduced-order models to efficiently analyze the whole system including the nonlinear drivers using conventional circuit simulation tools such as SPICE. The transfer characteristics of the power planes are calculated and the effects of the decoupling capacitors and power supply noise are studied. The simulation results are also correlated with measurement data to verify the validity of the method.

Jitter Amplification Considerations for PCB Clock Channel Design

Jitter Amplification is a real concern in the design of PCB clock channels if the frequency of the clock is high and the PCB trace is relatively long. In this paper, we confirm the earlier finding of clock channel jitter amplification [1], using a multiple edge response (MER) simulation method instead of jitter impulse response for the channel. However, we show that both white Random Jitter (wRJ) and Sinusoidal Jitter (SJ) amplification are a function of the signal loss in the channel, and as such, are reduced significantly with equalization. Furthermore, simulated CMOS Tx RJ, which is dominated by its low frequency components, is amplified less than is wRJ, even for channels with >20dB signal loss. Measurement results are correlated with simulations for 2-6 GHz clocks on a channel containing 24-inches of PCB trace.

Design and verification of differential transmission lines

Differential signaling is a popular choice for multi-gigabit digital applications such as FiberChannel, Infiniband, OIF, RapidIO, and XAUI. This is due to the fact that differential signaling has the ability to reject common mode noise such as cross talk, simultaneous switching noise, power supply and ground bounce noise. To support differential signaling, differential transmission lines are required. There are several ways of designing differential transmission lines on a conventional printed circuit board (PCB). These include microstrip line, edge coupled stripline, and broadside-coupled stripline. This paper describes a methodology for designing and verifying differential transmission lines on PCBs. The electrical performance of these three differential transmission lines is evaluated in both the frequency and time domain. The practical consideration of manufacturing variation is also examined. Finally, accurate HSPICE w-element models are generated for time domain transient simulations.

Investigating the Impact of Supply Noise on the Jitter in Gigabit I/O Interfaces

Minimizing the jitter due to supply noise is the most important design goal for the power delivery system of highspeed interfaces. We present a detailed analysis of supply noise induced jitter in a high-speed interface. We first simulate the supply noise spectrum generated in the interface. We then measure the sensitivity of the interface circuits to noise as a function of noise frequency. Next, we analyze the jitter spectrum by combining these two parameters. Based on this analysis, we observe large jitter contributions at medium frequencies. This is not expected if we consider only the supply noise current spectrum since the medium frequency is way below the data rate or the frequencies of internal clock signals. However, it can be easily explained with the power supply network impedance profile. Finally, we correlate the predicted jitter spectrum with the measured jitter spectrum of a serial link operating at 6.4 Gbps.

An Accurate Transient Analysis of High-Speed Package Interconnects Using Convolution Technique

An accurate transient analysis of a package interconnect requires the modeling and analysis of conductor and dielectric losses, as well as other high-frequency effects of 3D structures. The skin effect and dispersion of interconnects are more accurately modeled in frequency domain. Consequently, an accurate time-domain simulation of such a system is only possible using convolution techniques. Although the convolution method is well understood, the application of windowing for frequency-dependent interconnect analysis is less so. In this paper, we present the practical considerations of window selection and its application to improve the accuracy of convolution simulators. We introduce the Tukey window and study the tradeoff between how smoothly data can be set to zero to avoid aliasing and suppress ripples and how much information tapering will discount at the edge of the window in order to obtain meaningful results. The bandlimiting effects of the Tukey window and other well-known windows are also compared. Finally, to verify the validity and accuracy of the proposed method, a wirebond PBGA package and a PCB-connector system are analyzed using the scattering parameters obtained from simulation and measurement, respectively.

Prediction of System Performance Based on Component Jitter and Noise Budgets

Conventional ways of summing component specifications to balance voltage and timing budgets are increasingly problematic as data rates continue to scale higher for high speed links. For instance, performance degradation caused by transmitter jitter is more severe than that caused by receiver jitter due to jitter coloring by the passive channel. Furthermore, certain jitter components could interact in the system so it is inaccurate to treat them as independent variables. A system voltage and timing budgeting process hence requires a sophisticated method to accurately predict the overall system performance based on the component specifications. With the recent introduction of a statistical CAD tool, the impact of each individual component, including both deterministic and random jitter, can be co-simulated [l]-[3]. This paper demonstrates the usage of this statistical CAD tool for modeling component budgets. We verify the accuracy of our modeling approach by correlating with a FlexIOreg parallel link interface. Then, we apply the proposed methodology to a PCI Expressreg bus system to estimate the system performance based on published component jitter specification.

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration

The growing demand for low-power and high-fidelity chip-to-chip data communication has motivated the use of near-ground or low-common-mode voltage (LCM) signaling [1-2]. However, deployment of such signaling for high-speed applications such as graphics memory interfaces has been hampered by complications of the transmitter and receiver designs. Recent techniques have enhanced the performance of source-series terminated transmitters by accommodating impedance and equalization calibration at a low power cost [3]. This work advances LCM receiver high-frequency operation by introducing an accurate termination calibration, taking into account the receiver loading on the data link channel. Our receiver also incorporates common-mode-to-differential-gain cancellation and in-situ equalization calibration for reliable data reception at 16Gb/s over a 3” FR4 PCB memory link with 15dB loss at Nyquist frequency.