Chrissavgi Dre

Prime-factor DCT algorithms

In this correspondence, new algorithms are presented for computing the l-D and 2-D discrete cosine transform (DCT) of even length by using the discrete Fourier transform (DFT). A comparison of the proposed algorithms to other fast ones points out their computational efficiency, which is mainly based on the advantages of prime-factor decomposition and a proper choice of index mappings. >

The VLSI implementation of a baseband receiver for DECT-based portable applications

A digital area/power efficient VLSI implementation of the baseband part of a DECT demodulator, is introduced. Starting from algorithm level and after exhaustive architecture-level exploration employing low power design techniques and transformations, we conclude with the hardware implementation of four optimized algorithms. The proposed DECT receiver will be integrated with the processor ASPIS implementing the baseband signal processing of a multi-mode terminal GSM/DECT/DCS-1800.

On the computation of the prime factor DST

Abstract In this paper a new algorithm based on prime factor decomposition for computing the discrete sine transform (DST) is presented. The proposed 1-D N-point DST algorithm is indirectly computed by using the DFT. The DST of odd length can be implemented on the existing VLSI architectures of the DFT, while the DST of even length can be implemented on slightly modified DFT architectures. A comparison of the algorithm with other fast ones points out its computational efficiency, which is mainly based on the advantages of the prime factor decomposition and the proper choice of the index mappings.

On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal

For the implementation of a multi-mode DECT/GSM wireless terminal, a dual mode baseband processor, namely ASPIS processor, capable to undertake all baseband signal processing required is designed and fabricated. The multi-mode wireless terminal is based on direct conversion architecture. Experimental results from the operation of ASPIS processor and performance analysis of the selected architecture, under two different testing environments, are promising and quite satisfactory.

Low power design of a multi-mode transceiver

Recent advances in electronic technology integration coupled with increasing needs for more services in portable communications favors the development of high performance dual-mode terminals. We present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and A/D & D/A converters is also described in detail manner. The whole architecture of the modulator/demodulator was described by VHDL hardware language, synthesised and implemented in Xilinx environment.

Coding wavelet coefficients of images

In this paper, we introduce a new image compression scheme that involves three steps: first a multiresolution decomposition of the images is performed using the Wavelet Transform (WT). A thresholding algorithm is then used for the wavelet coefficients. Finally, the coefficients derived are vector quantized using the LGB or the Compressed Maximum Descent (CMD) algorithm.

Alternative architectures for the 2-D DCT algorithm

Recently, a new fast algorithm has been proposed for the computation of the 2-D N/spl times/N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N/sub 1/ and N/sub 2/. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity.

Compressed maximum descent algorithm for codebook generation

A vital step in building a vector quantizer is to generate an optimal codebook. Among the algorithms presented in the literature, the Maximum Descent (MD) algorithm appears to be a promising alternative codevector generation technique to the generalized Lloyd (LBG) algorithm, when dealing with vector quantization of images. In this paper, a novel vector quantization codebook generation approach is presented. The algorithm uses an MD codebook as an initial codebook and a compression of this codebook is then achieved based on a simple feature clustering technique. According to this technique, we attempt to arrange the codevectors of the MD codebook in a way that prefixed number of clusters results. The centroids of the resulted clusters form a reduced MD codebook. Using this new technique we can produce codebooks with about 0.2 - 0.6 db improvement in peak-signal to noise ratio and a reduction of 10% - 20% in the codebook size compared to the LBG algorithm.

The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal

In order to support a multimode DECT/GSM/DCS1800 terminal architecture, with low power characteristics and integrated support for direct conversion terminal architecture, the critical parts of such a terminal were designed and implemented using three different chips. These parts include a baseband processor, a modem and suitable analogue parts. The baseband processor was designed to support multimode operation, all baseband processing required and different terminal architectures (heterodyne or direct conversion). The modem features a GMSK/GFSK modulator and a novel, low power detection algorithm supports a direct conversion terminal. The analogue circuitry includes analogue filters and Digital-to-Analog and Analog-to-Digital converters. The architecture of the direct conversion wireless terminal is presented along with details on the low power characteristics of the processor and the modem. Experimental results from the operation of the multimode terminal are presented.

A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip

In this paper the design of a partly reconfigurable System-on-Chip (SoC) for wireless LANs is described. The reconfigurable System-on-Chip will realize both HIPERLAN/2 and IEEE 802.11a wireless LAN systems. The initial version of the system will include Mobile Terminal functionality. Future firmware versions will upgrade systems functionality to allow its operation as Access Point. Functionality for operation in outdoor environments in wireless point-to-point links will be also targeted by future firmware upgrades. A systems prototype is currently under development on the ARM integrator platform.